MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 369

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Address: Base + 0x004
Reset
Reset
HBERR
RFINT
TFINT
BABR
BABT
Field
GRA
RXB
TXB
MII
W
W
R
R
ERR
HB
16
0
0
0
0
BABR BABT GRA TFINT TXB
Heartbeat error.
This interrupt indicates HBC is set in the ETH_X_CNTRL register and the COL input was not asserted within
the heartbeat window following a transmission.
Babbling receive error.
This bit indicates a frame was received with length in excess of ETH_R_CNTRL[MAX_FL] bytes.
Babbling transmit error.
This bit indicates the transmitted frame length has exceeded ETH_R_CNTRL[MAX_FL] bytes. This condition
is usually caused by a frame that is too long being placed into the transmit data buffer(s). Truncation does not
occur.
Graceful stop complete.
This interrupt is asserted for one of three reasons. Graceful stop means that the transmitter is put into a pause
state after completion of the frame currently being transmitted.
Refer to
Transmit frame interrupt.
This bit indicates a frame has been transmitted and the last corresponding buffer descriptor has been updated.
Transmit buffer interrupt.
This bit indicates a transmit buffer descriptor that had the R bit set in its status word has been updated.
Receive frame interrupt.
This bit indicates a frame has been received and the last corresponding buffer descriptor has been updated.
Receive buffer interrupt.
This bit indicates a receive buffer descriptor that had the E bit set in its status word has been updated.
MII interrupt.
This bit indicates the MII has completed the requested data transfer.
• A graceful stop initiated by setting the GTS bit of the ETH_X_CNTRL register is now complete.
• A graceful stop initiated by setting the FC_PAUSE bit of the ETH_X_CNTRL register is now complete.
• A graceful stop initiated by the reception of a valid full-duplex flow control pause frame is now complete.
17
0
0
0
1
Section 14.6.4, “Full-Duplex Flow Control.”
18
0
0
0
2
Figure 14-3. Interrupt Event Register (ETH_IEVENT)
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-6. ETH_IEVENT field descriptions
20
4
0
0
0
21
0
0
0
5
INT
RF
22
0
0
0
6
RXB
23
0
0
0
7
Description
MII
24
8
0
0
0
ERR
EB
25
9
0
0
0
_COL
LATE
10
26
0
0
0
Y_LIM
RETR
COL_
11
27
0
0
0
Fast Ethernet Controller (FEC)
O_UN
XFIF
12
28
0
0
0
Access: User read/write
13
29
0
0
0
0
14
30
0
0
0
0
14-13
15
31
0
0
0
0