MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 700

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
25.4.1.12 Counter Timer Upper Register (CTUR)
This register holds the upper bytes of the preload value used by the timer to provide a given baud rate.
Reading from this register shows the current value of the baud rate generation counter. For a detailed
description, see
25.4.1.13 Counter Timer Lower Register (CTLR)
This register holds the lower bytes of the preload value used by the timer to provide a given baud rate.
Reading from this register shows the current value of the baud rate generation counter.
25-22
Address: Base + 0x28
Address: Base + 0x2C
CTUR
Reset
Reset
Field
W
W
R
R
Code. Frame Sync width, define the number of bit clocks during the FrameSync signal is active.
FrameSync Width equals CTUR[0:7] + 1.
UART/ SPI. Baud rate prescaler value.
See
Other. Reserved.
0
0
0
0
Section 25.4.1.13, “Counter Timer Lower Register (CTLR).”
Section 25.4.1.13, “Counter Timer Lower Register (CTLR).”
Figure 25-26. Counter Timer Upper Register for all Modes (CTUR)
Figure 25-27. Counter Timer Lower Register for all Modes (CTLR)
1
0
1
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 25-17. CTUR field descriptions
0
0
2
2
0
0
3
3
CTUR[0:7]
CTLR[0:7]
Description
0
0
4
4
0
0
5
5
Freescale Semiconductor
Access: User read/write
Access: User read/write
0
0
6
6
0
0
7
7