MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 572

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
LocalPlus Bus Controller (LPC)
Table 21-31
and 16-bit wide data buses. In addition, these tables show the influence of the WS and RS swap bits in the
Chip Select X Configuration Register.
1
2
The ALE signal is active low or high, depending on the ALE bit setting, and remains asserted for several
external LPC bus clocks, depending on the ALEN bit field setting. Any external latch should be
transparent when active.
21-32
WS or RS set
WS or RS set
Swap setting has no influence on byte transfers.
Data1 is the most significant byte and Data2 (2-byte transfer) or Data4 (4-byte transfer) is the least significant byte of the data
word.
Swap setting has no influence on byte transfers.
Data1 is most significant byte and Data2 is lowest significant byte of data word.
NO/YES
NO/YES
Swap
Swap
YES
YES
YES
NO
NO
NO
1
1
and
Other values are invalid and should not be required by the external device.
Transfer
Transfer
2 bytes
4 bytes
2 bytes
Table 21-32
1 byte
1 byte
Size
Size
Table 21-31. Aligned Data Transfers for 32-Bit Data Bus Width
Table 21-32. Aligned Data Transfers for 16-Bit Data Bus Width
TSIZ[1:0]
TSIZ0
01
10
00
describe the various combinations of TSIZ, address, and byte lanes for 32-bit
1
0
MPC5125 Microcontroller Reference Manual, Rev. 2
Address[1:0]
Address 0
00
00
00
01
10
11
10
00
10
0
1
0
NOTE
AD[31:24]
Data1
Data1
Data2
Data4
Data
—
—
—
—
—
2
AD[15:8]
Data1
Data2
Data
—
2
AD[23:16]
Data2
Data1
Data2
Data3
Data
—
—
—
—
—
Data Lanes
Data Lanes
AD[15:8]
Data1
Data2
Data3
Data2
Data
—
—
—
—
—
Freescale Semiconductor
AD[7:0]
Data2
Data1
Data
—
AD[7:0]
Data2
Data1
Data4
Data1
Data
—
—
—
—
—