MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 202

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
CSB Arbiter and Bus Monitor
transactions can be limited by programming the Arbiter Configuration Register (See
“Arbiter Configuration Register (ACR),”
8.2
Table 8-1
8.2.1
8.2.1.1
The Arbiter Configuration Register (ACR) defines the arbiter modes and parked master on the bus.
Figure 8-1
8-2
(0xFF40_0D00)
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
In this column, R/W = Read/Write, R = Read-only, and W = Write-only.
In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated description for
more information.
ARB_BASE
Offset from
0x24–0xFF
0x0C
0x1C
0x00
0x04
0x08
0x10
0x14
0x18
0x20
Memory Map/Register Definition
shows the memory map for arbiter’s configuration, control and status registers.
shows the fields of ACR.
Register Descriptions
Arbiter Configuration Register (ACR)
1
ACR—Arbiter Configuration Register
ATR—Arbiter Timers Register
ATER—Arbiter Transfer Error Register
AER—Arbiter Event Register
AIDR—Arbiter Interrupt Definition Register
AMR—Arbiter Mask Register
AEATR—Arbiter Event Attributes Register
AEADR—Arbiter Event Address Register
AERR—Arbiter Event Response Register
Reserved
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 8-1. Arbiter memory map
Register
for more details).
Chapter 2, “System Configuration and Memory
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
2
0xFFFF_FFFF
0x0UU0_0000
0x0000_003F
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Freescale Semiconductor
Section 8.2.1.1,
3
Section/Page
8.2.1.8/8-11
8.2.1.9/8-12
8.2.1.1/8-2
8.2.1.2/8-4
8.2.1.3/8-5
8.2.1.4/8-6
8.2.1.5/8-7
8.2.1.6/8-8
8.2.1.7/8-9