MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 514

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Inter-Integrated Circuit (I
This filter can absorb glitches on the I
to absorb is specified in terms of number of IPS clock cycles. This glitch filter control register is provided
for all three I
The programming of the glitch filter is simple; the programmer only needs to specify the size of glitch (in
terms of IPS cycles) for the filter to absorb and not pass.
19.4
Reset puts the I
following initialization procedure must be done:
Update the frequency divider register and select the required division ratio to obtain the SCL frequency
from the IPS clock.
Update the I
Set the control register EN bit to enable the I
Modify the control register bits to select master/slave mode, transmit/receive mode, and interrupt enable
or not.
19-22
1. Calculate the divider according to the ips clock frequency and the expected SCL frequency:
2. Look in
3. Set the prescaler in frequency divider register equal to FDR obtain from look-up table.
FR[7:4]
Field
scl_divider = f_IPS/f_SCL.
register according to the calculated divider.
Initialization Sequence
2
2
C address register to define a slave address.
C modules.
Bits 7 to 4 contain the programming controls for the width of glitch (in terms of IPS clock cycles) the filter should
absorb; in other words, the filter does not let glitches less than or equal to this width setting pass.
0000 No Filter/Bypass
0001 Filter glitches as wide as 1 IPS clock cycle.
0010 Filter glitches as wide as 2 IPS clock cycles.
0011 Filter glitches as wide as 3 IPS clock cycles.
0100 Filter glitches as wide as 4 IPS clock cycles.
0101 Filter glitches as wide as 5 IPS clock cycles.
0110 Filter glitches as wide as 6 IPS clock cycles.
0111 Filter glitches as wide as 7 IPS clock cycles.
1000 Filter glitches as wide as 8 IPS clock cycles.
1001 Filter glitches as wide as 9 IPS clock cycles .
1010 Filter glitches as wide as 10 IPS clock cycles .
1011 Filter glitches as wide as 11 IPS clock cycles.
1100 Filter glitches as wide as 12 IPS clock cycles.
1101 Filter glitches as wide as 13 IPS clock cycles.
1110 Filter glitches as wide as 14 IPS clock cycles.
1111 Filter glitches as wide as 15 IPS clock cycles.
2
Table 19-6
C control register to its default status. Before the interface can transfer serial data, the
2
C)
to find out value of the Frequency Divider Bit (FDR) in the I2C_MFDRn
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 19-11. I2C_MIFR field descriptions
2
C clock and data lines for each I
2
C interface system.
Description
2
C module. The width of the glitch
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