MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 856

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.2.4.7
For the OTG module in device mode, the upper 7 bits of the Device Address (USB_DEVICEADDR)
register represent the device address. After any controller reset or a USB reset, the device address is set to
the default address (0). The default address matches all incoming addresses. Software reprograms the
address after receiving a SET_ADDRESS descriptor.
The USBADRA can accelerate the SET_ADDRESS sequence by allowing the DCD to preset the
USBADR register before the status phase of the SET_ADDRESS descriptor.
On the OTG module, this register is shared between the host and device mode functions. In device mode,
it is the USB_DEVICEADDR register; in host mode, it is the USB_PERIODICLISTBASE register. See
Section 32.2.4.6, “Periodic Frame List Base Address (USB_PERIODICLISTBASE) Register,”
information. This register is not defined in the EHCI specification.
32-28
Address: Base + 0x154
Address: Base + 0x154
PERBASE
Reset
Reset
Reset
Reset
Field
W
W
W
W
R
R
R
R
Figure 32-20. Periodic Frame List Base Address (USB_PERIODICLISTBASE) Register
16
16
0
0
0
0
0
0
0
PERBASE (cont.)
Device Address (USB_DEVICEADDR) Register (Non-EHCI)
Base Address. These bits correspond to memory address signal [31:12]. Only used in the host mode.
17
17
0
0
0
0
0
1
1
18
18
Figure 32-21. Device Address (USB_DEVICEADDR) Register
0
0
0
0
0
2
2
Table 32-21. USB_PERIODICLISTBASE field descriptions
USBADR
19
19
0
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
20
20
4
0
0
0
4
0
0
0
21
21
0
0
0
0
0
0
5
5
22
22
0
0
0
0
0
0
6
6
USBA
DRA
PERBASE
23
23
0
0
0
0
0
0
7
7
Description
24
24
8
0
0
0
8
0
0
0
0
25
25
9
0
0
0
9
0
0
0
0
10
26
10
26
0
0
0
0
0
0
0
11
27
11
27
0
0
0
0
0
0
0
12
28
12
28
0
0
0
0
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
13
29
13
29
0
0
0
0
0
0
0
14
30
14
30
0
0
0
0
0
0
0
for more
15
31
15
31
0
0
0
0
0
0
0