MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 915

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.6.6
The structure of an iTD is presented in
(iTD).”
32.6.6.1
The host controller uses USB_FRINDEX[12:3] to index into the periodic frame list. This means the host
controller visits each frame list element eight consecutive times before incrementing to the next periodic
frame list element. Each iTD contains eight transaction descriptions that map directly to
USB_FRINDEX[2:0]. Each iTD can span eight micro-frames worth of transactions. When the host
controller fetches an iTD, it uses USB_FRINDEX[2:0] to index into the transaction description array. If
the active bit in the status field of the indexed transaction description is cleared, the host controller ignores
the iTD and follows the next pointer to the next schedule data structure.
When the indexed active bit is a one, the host controller continues to parse the iTD. It stores the indexed
transaction description and the general endpoint information (device address, endpoint number, maximum
Freescale Semiconductor
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The first field is the next link pointer. This is for schedule linkage purposes only.
Transaction description array. This area is an eight-element array. Each element represents control
and status information for one micro-frame’s worth of transactions for a single high-speed
isochronous endpoint.
The buffer page pointer array is a 7-element array of physical memory pointers to data buffers.
These are 4K aligned pointers to physical memory.
Endpoint capabilities. This area utilizes the unused low-order 12 bits of the buffer page pointer
array. The fields in this area are used across all transactions executed for this iTD, including
endpoint addressing, transfer direction, maximum packet size, and high-bandwidth multiplier.
There are four distinct sections to an iTD:
1024, 512, or 256
Managing Isochronous Transfers Using iTDs
Host Controller Operational Model for iTDs
Elements
Periodic Frame List
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 32-55. Example Periodic Schedule
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•
•
Section 32.5.3, “Isochronous (High-Speed) Transfer Descriptor
Poll Rate: 1
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A
A
A
A
A
A
Poll Rate: N –– > 1
8
Isochronous Transfer
Descriptor(s)
A
Universal Serial Bus Interface with On-The-Go
4
• • •
1
Last
Periodic has
End of
List Mark
Interrupt Queue
Heads
32-87