MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 911

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

information. The USB_PERIODICLISTBASE register is the physical memory base address of the
periodic frame list. The periodic frame list is an array of physical memory pointers. The objects referenced
from the frame list must be valid schedule data structures as defined in
Structures.”
from the periodic schedule before executing from the asynchronous schedule. It only executes from the
asynchronous schedule after it encounters the end of the periodic schedule. The host controller traverses
the periodic schedule by constructing an array offset references from the USB_PERIODICLISTBASE and
the USB_FRINDEX registers (see
linked schedule data structures.
The end of the periodic schedule is identified by a next link pointer of a schedule data structure having its
T-bit set. When the host controller encounters a T-Bit set during a horizontal traversal of the periodic list,
it interprets this as an End-Of-Periodic-List mark. This causes the host controller to cease working on the
periodic schedule and transition immediately to traversing the asynchronous schedule. After this transition
is made, the host controller executes from the asynchronous schedule until the end of the micro-frame.
When the host controller determines it is time to execute from the asynchronous list, it uses the operational
USB_ASYNCLISTADDR register to access the asynchronous schedule, as shown in
The USB_ASYNCLISTADDR register contains a physical memory pointer to the next queue head. When
the host controller makes a transition to executing the asynchronous schedule, it begins by reading the
Freescale Semiconductor
31
In each micro-frame, if the periodic schedule is enabled, then the host controller must execute
USB_ASYNCLISTADDR
31
Periodic Frame List Base
USB_USBCMD
USB_USBSTS
Operational
Registers
Address
Figure 32-52. General Format of Asynchronous Schedule List
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•
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•
•
•
Figure 32-51. Derivation of Pointer into Frame List Array
MPC5125 Microcontroller Reference Manual, Rev. 2
Periodic Frame List Element
Figure
Doubleword-Aligned
32-51). It fetches the element and begins traversing the graph of
Address
12
13 12
12 11
Frame Index Register
H
Universal Serial Bus Interface with On-The-Go
3 2
Section 32.5, “Host Data
2 1 0
0
Periodic Frame
Figure
List
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32-52.
32-83