MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 94

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset
1
2
4.6
The reset configuration and status registers are shown in
4-8
10
11
12
13
14
(0xFF40_0E00)
4
5
6
7
8
9
Care must be taken to ensure that the IMMR address region does not overlap any active access windows at any time during
the boot process.
This MUST be changed to cache inhibited prior to entry into user code space.
RESET_BASE
Offset from
0x08–0x0F
0x24–0xFF
Initialize DRAM
Copy NFC bootstrap to DRAM
Perform absolute jump to NFC
bootstrap
Initialize Memory Map
Code re-location
Initialize e300 Core
Initialize system clocks
Initialize IO pin muxing
c-runtime initialization
peripheral initialization
Boot Into Application Space
0x1C
0x00
0x04
0x10
0x14
0x18
0x20
Memory Map
1
Step
Reset Configuration Word Low (RCWL) Register
Reset Configuration Word High (RCWH) Register
Reserved
Reset Status Register (RSR)
Reset Mode Register (RMR)
Reset Protection Register (RPR)
Reset Control Register (RCR)
Reset Control Enable Register (RCER)
Reserved
Table 4-7. Reset Configuration Registers Memory Map
Table 4-6. NFC Initialization Sequence (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
Reset Vector (Flash)
Reset Vector (Flash)
NFC Bootstrap (DRAM) Relative branch should not be used.
Startup (DRAM)
Startup (DRAM)
Startup (DRAM)
Startup (DRAM)
Startup (DRAM)
Startup (DRAM)
Startup (DRAM)
(DRAM)
Software Region
Register
Initialization should include DRAM access window as well
as timings and initialization
Initialize all memory access windows and LPC chip selects
Relocate code into DRAM for faster execution. Must use
nand flash mini-driver to access NAND flash
Initialize core settings including cache policies and
instruction burst capabilities. Flash should be initialized as
both I/D cached in copyback mode
This allows remaining routines
Perform any initialization required by monitor or RTOS here.
Start Application Environment (RTOS)
Table
4-7.
Access
R/W
R/W
R/W
R/W
R/W
R
R
0x0U0U_0U00
0xUUU0_UU00
Note
0x0000_0000
Reset Value
0x6000_0000
0x0000_0000
0x0000_0000
0x0000_0000
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Freescale Semiconductor
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Section/Page
4.6.3/4-10
4.6.4/4-12
4.6.5/4-13
4.6.6/4-13
4.6.7/4-14
4.6.1/4-9
4.6.2/4-9