MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 975

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.7
This section defines the interface data structures that communicate control, status, and data between device
controller driver (DCD) software and the device controller. Data structure definitions in this chapter
support a 32-bit memory buffer address space. The interface consists of device queue heads and transfer
descriptors.
The data structures defined in this section are (from the device controller's perspective) a mix of read-only
and read/writable fields. The device controller must preserve the read-only fields on all data structure
writes.
The USB core includes DCD software called the USB 2.0 device API. The device API provides an easy
to use application program interface for developing device (peripheral) applications. The device API
incorporates and abstracts for the application developer all of the elements of the program interface.
32.7.1
The device Endpoint Queue Head (dQH) is where all transfers are managed. The dQH is a 48-byte data
structure, but must be aligned on 64-byte boundaries. During priming of an endpoint, the dTD (device
Freescale Semiconductor
ENDPOINTLISTADDR
Device Data Structures
Endpoint Queue Head
Up to
32 elements
This bitmap needs to be redrawn
Software must ensure no interface data structure reachable by the device
controller spans a 4K-page boundary.
Figure 32-71. End Point Queue Head Organization
MPC5125 Microcontroller Reference Manual, Rev. 2
Endpoint QH 1
Endpoint QH 0
Endpoint QH 0
– Out
– In
– Out
NOTE
Endpoint Queue Heads
Transfer
Buffer
Pointer
Transfer Buffer Pointer
Transfer Buffer Pointer
Endpoint
Transfer
Descriptor
Universal Serial Bus Interface with On-The-Go
Transfer
Buffer
Transfer Buffer
Pointer
Transfer
Buffer
Transfer
Buffer
Transfer
Buffer
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