MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 368

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
14.3.5.2
When an event occurs that sets a bit in the Interrupt Event (ETH_IEVENT) register, an interrupt is
generated if the corresponding bit in the Interrupt Enable (ETH_IMASK) register is also set. The bit in the
interrupt event register is cleared if a 1 is written to that bit position. Writing 0 has no effect. This register
is cleared upon hardware reset.
These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and
internal error interrupts. Interrupts that may occur in normal operation are GRA, TFINT, TXB, RFINT,
RXB, and MII. Interrupts resulting from errors/problems detected in the network or transceiver are
HBERR, BABR, BABT, LATE_COL and COL_RETRY_LIM. Interrupts resulting from internal errors
are EBERR and XFIFO_UN.
Some of the error interrupts are independently counted in the MIB block counters. Software may choose
to mask off these interrupts because these errors are visible to network management via the MIB counters.
14-12
FEC_REV
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FEC_ID
Field
FIFO
DMA
SMII
HBERR—ieee_t_sqe
BABR—rmon_r_oversize (good CRC), rmon_r_jab (bad CRC)
BABT—rmon_t_oversize (good CRC), rmon_t_jab (bad CRC)
LATE_COL—ieee_t_lcol
COL_RETRY_LIM—ieee_t_excol
XFIFO_UN—ieee_t_macerr
Interrupt Event Register (ETH_IEVENT)
Unique identifier for FEC.
0000
DMA function included in the FEC
0 EC does not include DMA.
1 FEC includes DMA (ETH_DMA_CONTROL register contains DMA revision).
FIFO function included in the FEC
0 FEC does not include a FIFO.
1 FEC includes a FIFO (FIFO_ID register contains the FIFO revision).
The Ethernet PHY interface configuration.
1 SMII (serial MII) interface. This 6-pin serial MII option requires that the MII_MODE bit of the
0 MII (18 pins) or 7-wire (select MII or 7-wire via the MII_MODE bit of the ETH_R_CNTRL register).
Value identifies the revision of the FEC.
00 Initial revision.
ETH_R_CNTRL register is set equal to 1.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-5. ETH_FEC_ID field descriptions
Description
Freescale Semiconductor