MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 374

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
1
Write the ETH_MII_DATA register to perform a read or write operation on the MII management interface.
To generate a valid read or write management frame, the ST field must be written with a 01 pattern, the
OP field must be written with a 01 (management register write frame) or 10 (management register read
frame), and the TA field must be written with a 10. If other patterns are written to these fields, a frame is
generated, but does not comply with the IEEE 802.3 MII definition. When op field equals 1x, it produces
a read-frame operation, while op equals 0x produces a write-frame operation.
To generate an 802.3-compliant MII management interface write frame (write to a PHY register), write
{01 01 PHYAD REGAD 10 DATA} to the ETH_MII_DATA register. Writing this pattern causes the
control logic to shift out the data in the ETH_MII_DATA register following a preamble generated by the
control state machine. During this time, the contents of the ETH_MII_DATA register is altered as the
contents are serially shifted, and are unpredictable if read by the user. The MII interrupt is generated after
the write management frame operation has been completed. At this time, the contents of the
ETH_MII_DATA register match the original value written.
To generate an MII management interface read frame (read a PHY register), write {01 10 PHYAD REGAD
10 XXXX} to the ETH_MII_DATA register (the content of the data field is a “don’t care”). Writing this
pattern causes the control logic to shift out the data in the ETH_MII_DATA register following a preamble
generated by the control state machine. During this time, the contents of the ETH_MII_DATA register are
altered as the contents are serially shifted and are unpredictable if read. The MII interrupt is generated after
14-18
Address: Base + 0x040
This register is undefined at reset.
Reset
Reset
Field
DATA
OP
RA
ST
W
W
PA
TA
R
R
1
—
—
16
0
ST
Start of frame delimiter. These bits must be programmed to 0b01 for a valid MII management frame.
Operation code. This field must be programmed to 0b10 (read) or 0b01(write) to generate a valid MII
management frame. A value of 11 produces read frame operation, while a value of 00 produces write frame
operation, but these frames are not MII-compliant.
PHY address. This field specifies one of as many as 32 attached PHY devices.
Register address. This field specifies one of as many as 32 registers within the specified PHY device.
Turn around. This field must be programmed to 0b10 to generate a valid MII management frame.
Management frame data. This is the field for data to be written to or read from the PHY register.
—
—
17
1
Figure 14-8. MII Management Frame (ETH_MII_DATA) Register
—
—
18
2
OP
—
19
—
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-11. ETH_MII_DATA field descriptions
—
—
20
4
—
—
21
5
PA
—
—
22
6
—
—
23
7
DATA
Description
—
—
24
8
—
—
25
9
—
—
10
26
RA
—
—
11
27
—
—
12
28
Freescale Semiconductor
Access: User read/write
—
—
13
29
—
—
14
30
TA
—
—
15
31