MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 140

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1
2
3
Byte Data Link Controller (BDLC)
6.3.2
6-4
DLCBSVR
DLCBARD
DLCBRSR
DLCBCR1
DLCBCR2
(0xFF40_1400)
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
In this column, R/W = Read/Write, R = Read-only, and W = Write-only.
In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated description for
more information.
DLCBDR
DLCSCR
BDLC_
BDLC_
BDLC_
BDLC_
BDLC_
BDLC_
BDLC_
BDLC_BASE
Offset from
0x0C
0x00
0x01
0x04
0x05
0x08
0x09
0x0A–0x0B
0x0E–0xFF
0x06–0x07
0x0C
0x0D
Name
0x08
0x09
Register Summary
W
W
W
W
W
W
W
R
R
R
R
R
R
R
1
Reserved
BDLC Analog Round Trip Delay Register (BDLC_DLCBARD)
BDLC Rate Select Register (BDLC_DLCBRSR)
Reserved
BDLC Control Register (BDLC_DLCSCR)
BDLC Status Register (BDLC_DLCBSTAT)
Reserved
SMRST
IMSG
D7
R7
0
0
0
7
MPC5125 Microcontroller Reference Manual, Rev. 2
DLOOP
RXPOL
CLKS
Table 6-2. BDLC memory map (continued)
D6
R
0
0
6
Table 6-3. BDLC Register Summary
Register
4XE
D5
R5
I3
0
0
0
5
BDLCE
NBFS
BO4
D4
R4
I2
4
0
TEOD
BO3
D3
R3
I1
0
0
3
Chapter 2, “System Configuration and Memory
Access
R/W
R/W
R/W
R/W
TSIFR
BO2
2
D2
R2
I0
2
0
0
Reset Value
0x50
0x00
0x00
0x00
Freescale Semiconductor
TMIFR1
BO1
D1
R1
IE
0
0
1
3
Section/Page
6.3.2.5/6-14
6.3.2.6/6-16
6.3.2.7/6-17
6.3.2.8/6-18
TMIFR0
BREAK
BO0
D0
R0
0
0
0