MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 166

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Byte Data Link Controller (BDLC)
240 µs
Active
(2) Valid BREAK Symbol
Passive
T
rv6(Min)
Figure 6-16. J1850 VPW BREAK Symbol
Valid BREAK Symbol
If the next active to passive transition does not occur until after T
, the current symbol is considered
rv6(Min)
a valid BREAK symbol. A BREAK symbol should be followed by a SOF symbol beginning the next
message to be transmitted onto the J1850 bus. See
Figure
6-16.
6.4.2.10.2
Message Arbitration
Message arbitration on the J1850 bus is accomplished in a non-destructive manner, allowing the message
with the highest priority to be transmitted, while any transmitters that lose arbitration stop transmitting and
wait for an idle bus to begin transmitting again.
If the BDLC module wishes to transmit onto the J1850 bus, but detects that another message is in progress,
it automatically waits until the bus is idle. However, if multiple nodes begin to transmit in the same
synchronization window, message arbitration occurs beginning with the first bit after the SOF symbol and
continue with each bit thereafter.
The VPW symbols and J1850 bus electrical characteristics are carefully chosen so that a logic zero (active
or passive type) always dominates over a logic one (active or passive type) simultaneously transmitted.
Hence logic zeroes are said to be dominant and logic ones are said to be recessive.
When a node transmits a recessive bit and detects a dominant bit, it loses arbitration, and immediately stops
transmitting. This is known as bitwise arbitration. The loss of arbitration flag in the BDLC_DLCBSVR
register is set when arbitration is lost. If the interrupt enable bit (IE in the BDLC_DLCBCR1 register) is
set, an interrupt request from the BDLC module is generated. Reading the BDLC_DLCBSVR register
clears this flag.
During arbitration, or even throughout the transmitting message, when an opposite bit is detected,
transmission is immediately stopped unless it occurs on the eighth bit of a byte. In this case, the BDLC
module automatically appends as many as two extra 1 bits and then stops transmitting. These two extra
bits are arbitrated normally and thus do not interfere with another message. The second 1 bit is not sent if
the first loses arbitration. If the BDLC module has lost arbitration to another valid message, the two extra
1s do not corrupt the current message. However, if the BDLC module has lost arbitration due to noise on
the bus, the two extra 1s ensure the current message is detected and ignored as a noise-corrupted message.
MPC5125 Microcontroller Reference Manual, Rev. 2
6-30
Freescale Semiconductor