MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 412

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

General Purpose Timers (GPT)
15.1.1.2
In Output Compare mode, the I/O pin is an Output. When enabled, the counters run until they reach the
programmed Terminal Count value. At this point, the specified output event is generated (toggle, pulse
high, or pulse low). If enabled, a CPU interrupt is generated.
15.1.1.3
In PWM mode, the I/O pin is an Output. The user can program period and width values to create an
adjustable, repeating output waveform on the I/O pin. A CPU interrupt can be generated at the beginning
of each PWM Period, at which time a new Width value can be loaded. The new Width value, which
represents ON time, is automatically applied at the beginning of the next period. There is no interrupt at
the beginning of the first PWM Period. This mode is suitable for PWM audio encoding. The GPT can
support a combination of PWM outputs.
15.1.1.4
In Simple GPIO mode, the I/O pin operates as a GPIO pin. It can be specified as Input or Output, according
to the programmable GPIO field. GPIO mode is mutually exclusive of Input Capture, Output Compare,
and PWM modes.
15.1.1.5
In CPU Timer mode, the I/O pin is not used. Once enabled, the counters run until they reach a programmed
Terminal Count. When this occurs, an interrupt can be generated to the CPU. This timer mode can be used
simultaneously with the Simple GPIO mode.
15.1.2
Table 15-1
15.2
Each GPT timer channel uses four 32-bit registers.
registers. Within each GPTimer module, the registers are numbered to correspond to the pin for the
respective timer channel.
15-2
GPTn[0:7]
Signal
Memory Map and Register Definition
provides detailed descriptions of the external GPTimer signals.
Detailed Signal Descriptions
Output Compare
PWM
Simple GPIO
CPU Timer
I/O
I/O
GPTimer n 0–7. Each GPTimer module provides eight pins, numbered 0 through 7. Each pin can be
individually set to act as input or output, according to application needs.
Meaning
Table 15-1. GPT External Signals—Detailed Signal Descriptions
Timing Assertion/Negation —Inputs can be asserted completely asynchronously.
State
MPC5125 Microcontroller Reference Manual, Rev. 2
Asserted/Negated—Defined per application.
Outputs are asynchronous to any externally visible clock
Table 15-2
Description
shows the memory map for the local access
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