MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 991

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.8.5.2
All requests to a control endpoint begin with a setup phase followed by an optional data phase and a
required status phase. The USB controller always accepts the setup phase unless the setup lockout is
engaged.
The setup lockout engages so future setup packets are ignored. Lockout of setup packets ensures that while
software is reading the setup packet stored in the queue head, data is not written as it is being read
potentially causing an invalid setup packet.
The setup lockout mechanism can be disabled and a tripwire type semaphore ensures the setup packet
payload is extracted from the queue head without being corrupted by an incoming setup packet. This is
preferred behavior because ignoring repeated setup packets due to long software interrupt latency would
be a compliance issue.
Setup Packet Handling:
Following the setup phase, the DCD must create a device transfer descriptor for the data phase and prime
the transfer.
After priming the packet, the DCD must verify a new setup packet has not been received by reading the
USB_ENDPTSETUPSTAT register immediately verifying that the prime had completed. A prime
completes when the associated bit in the USB_ENDPTPRIME register is 0 and the associated bit in the
USB_ENDPTSTATUS register is 1. If a prime fails, i.e., the USB_ENDPTPRIME bit goes to zero and the
USB_ENDPTSTATUS bit is not set, then the prime has failed. This can only be due to improper setup of
the dQH, dTD or a setup arriving during the prime operation. If a new setup packet is indicated after the
Freescale Semiconductor
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Disable setup lockout by writing 1 to setup lockout mode (SLOM) in the USB_USBMODE
register (once at initialization). Setup lockout is not necessary when using the tripwire as described
below.
After receiving an interrupt and inspecting the USB_ENDPTSETUPSTAT register to determine
that a setup packet was received on a particular pipe:
— Write 1 to clear corresponding bit in the USB_ENDPTSETUPSTAT register.
— Write 1 to setup TripWire (SUTW) in the USB_USBCMD register.
— Duplicate contents of dQH.SetupBuffer into local software byte array.
— Read setup TripWire (SUTW) in USB_USBCMD register. (if set - continue; if cleared - goto 2)
— Write 0 to clear setup Tripwire (SUTW) in USB_USBCMD register.
— Process setup packet using local software byte array copy and execute status/handshake phases.
Control Endpoint Operation Model
Leaving the setup lockout mode as 0 results in a potential compliance issue.
After receiving a new setup packet, the status and/or handshake phases may
be pending from a previous control sequence. These should be flushed and
de-allocated before linking a new status and/or handshake dTD for the most
recent setup packet.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
NOTE
Universal Serial Bus Interface with On-The-Go
32-163