MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 631

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 23
NAND Flash Controller (NFC)
23.1
Composed of various control logic units and a 9 KB SRAM buffer, the NAND Flash Controller (NFC)
implements the interface to standard NAND flash memory devices. See
of the NFC.
Freescale Semiconductor
boot_after_reset
ipg_clk
ips_clk
reset_b
Introduction
boot_done
CMD
DATA
Control
Register
Config
DMA Bus
Boot
Control
DMA
Control
Addr
Dec.
boot_fail
MPC5125 Microcontroller Reference Manual, Rev. 2
boot_mode
Figure 23-1. NFC Block Diagram
BCH Encoder
7 ECC Modes
ECC Control
Residue
Generation
Control
BCH
Decoder
SRAM
Control
SRAM buffer
9 KB
Figure 23-1
SRAM
buffer
BUS
for a block diagram
NFC_IO[15:0]
NFC_ALE
NFC_WE
NFC_R/Bn
NFC_CLE
NFC_RE
REQ
IDLE
NFC_CEn
GRT
irq
23-1