MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 988

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
considered. For example, if endpoint 3 (transmit direction) is configured as a bulk pipe, you can expect the
host to send IN requests to that endpoint. The device controller prepares packets for each
endpoint/direction in anticipation of the host request. The process of preparing the device controller to
send or receive data in response to host initiated transaction on the bus is referred to as priming the
endpoint. This term appears throughout the following documentation to describe the device controller
(USB controller) operation so the DCD can be architected properly use priming. Further, the term flushing
describes the action of clearing a packet queued for execution.
Priming a transmit endpoint causes the device controller to fetch the device transfer descriptor (dTD) for
the transaction pointed to by the device queue head (dQH). After the dTD is fetched, it is stored in the dQH
until the device controller completes the transfer described by the dTD. Storing the dTD in the dQH allows
the device controller to fetch the operating context needed to manage a request from the host without the
need to follow the linked list, starting at the dQH when the host request is received.
After the device has loaded the dTD, the leading data in the packet is stored in a FIFO in the device
controller.
After a priming request is complete, an endpoint state of primed is indicated in the USB_ENDPTSTATUS
register. For a primed transmit endpoint, the device controller can respond to an IN request from the host
and meet the stringent bus turnaround time of High Speed USB.
Because only the leading data is stored in the device controller FIFO, it is necessary for the device
controller to begin filling in behind leading data after the transaction starts. The FIFO must be sized to
account for the maximum latency that can be incurred by the system memory bus.
Priming receive endpoints are identical to priming of transmit endpoints from the point of view of the
DCD. At the device controller, the major difference in the operational model is no data movement of the
leading packet data simply because the data is to be received from the host.
As part of the architecture, the FIFO for the receive endpoints is not partitioned into multiple channels like
the transmit FIFO. Therefore, the size of the RX FIFO does not scale with the number of endpoints.
32.8.5.1
The behaviors of the device controller for interrupt and bulk endpoints are identical. All valid IN and OUT
transactions to bulk pipes handshake with a NAK unless the endpoint had been primed. After the endpoint
has been primed, data delivery commences.
A dTD is retired by the device controller when the packets described in the transfer descriptor have been
completed. Each dTD describes n packets to be transferred according to the USB variable length transfer
protocol. The formula and table on the following page describes how the device controller computes the
number and length of the packets to be sent/received by the USB vary according to the total number of
bytes and maximum packet length.
With Zero Length Termination (ZLT) = 0
With Zero Length Termination (ZLT) = 1
32-160
N = INT(Number Of Bytes/Max. Packet Length) + 1
N = MAXINT(Number Of Bytes/Max. Packet Length)
Interrupt/Bulk Endpoint Operational Model
MPC5125 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor