MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 214

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

CSB Arbiter and Bus Monitor
Figure 8-11
example, if all masters request the bus continuously, the following order of bus grants occurs with the
specific bandwidth:
8.3.1.2
When a master owns the current address bus and wants to perform another transaction, it can assert bus
request along with REPEAT, to make a repeat request to the arbiter. Consequently, the arbiter asserts bus
grant to the same master if the current address tenure is not being ARTRY’d. This happens regardless of
the priority level of bus request from other masters. In other words, repeat request overrides the priority
scheme.
Even though repeat request can improve the page hit ratio and the overall memory bandwidth efficiency,
it can increase the worst case latency of individual master. Therefore, the arbiter has a programmable
8-14
2. For every priority level other than 0, one place is reserved as a place holder for lower level
3. Each master can change its priority level at any time.
•
•
•
•
arbitration rings.
M6 gets 1/2 of the bus bandwidth
M4 and M5 each get 1/6 of the bus bandwidth
M0 and M3 each get 1/18 of the bus bandwidth
M1 and M2 each get 1/36 of the bus bandwidth
shows an example of priority based arbitration algorithm with four priority levels. In this
Address Bus Arbitration With REPEAT
Z
Y
X
Figure 8-11. Example of Priority Based Arbitration Algorithm
MPC5125 Microcontroller Reference Manual, Rev. 2
M6
M4
M0
M1
Level 3
Level 2
Level 1
Level 0
M5
M3
M2
M6
M6
M6
M6
M6
M6
M4 M5
M4 M5
M4 M5
M0 M3
M0 M3
M1 M2 M1 M2 ...
Z
M4
M5
M1
M4
M5
M6
M6
M6
M6
M6
M6
Y
M0
M0
X
M1
Z
M4 M5
M0 M3
M5
M3
M4
M5
M2
M4 M5
M4 M5
M0 M3
...
M6
M6
M6
M6
...
Y
X
M0
M4
M5
M3
M3
M3
M2
...
...
M6
M6
M6
M6
M4 M5
M4 M5
M0 M3
M4
M5
M0
M4
M1
M2
M1
Freescale Semiconductor
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