MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 90

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Reset
4.4
SRESET provides a mechanism to shorten the boot flow by bypassing initialization of boot peripherals
and clocks (see
Sheet.
4.4.1
The following sources initiate an SRESET sequence:
4.4.2
When SRESET sequence is initiated, the following occurs:
4.5
The RST_CONF word is latched 3 oscillator clock cycles after PORESET is deasserted. This controls the
boot configuration of the device. Each RST_CONF pin MUST have external pull-up/pull-down devices
that ensure that the device enters the desired mode of operation. The value latched into the device at reset
may be verified by access to the RCWLR and RCWHR registers (see
Available modes include:
4-4
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Real time clock shadow registers and time, date, alarm, and stopwatch registers initialize to reset
state. Other RTC registers are not reset.
SRESET input signal
JTAG JSRS command
Software write to the RESET module
SRESET pin is asserted by the device
The following peripherals are not affected by reset:
— IO control and pin multiplexing
— Clock control registers
— Memory access windows (XLBMEN)
— Local plus memory controller (LPC)
— DRAM controller (MDDRC)
— RTC registers on the V
Reset source is captured in the RESET module
MSR[IP] bit in the e300 core is not updated
The e300 core starts execution at the reset vector
See e300 core manual for core impact of SRESET
Test modes
Boot interface selection
SRESET Flow
Reset Configuration Word (RST_CONF)
Sources
Impacts
Table
4-1). Timing for SRESET can be found in the MPC5125 Microcontroller Data
MPC5125 Microcontroller Reference Manual, Rev. 2
BAT
power domain (see
Section 4.5.2, “RTC at
Section 4.6, “Memory
Reset”)
Freescale Semiconductor
Map”).