MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 791

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When an interrupt is generated, there may be some error bits in the STATUS register set and the pending
interrupt status (source of the interrupt must be cleared). Check the error status bit to make sure there is no
error in the SDHC operation. For example, when the STATUS[READ_OP_DONE] status is set or the
READ_OP_DONE interrupt is detected, check the STATUS[READ_CRC_ERR] and
STATUS[TIME_OUT_READ] bits to make sure the read operation completed without a CRC error or a
time out error. Another example is a write operation, if both the STATUS[WRITE_OP_DONE] and
STATUS[WRITE_CRC_ERR2] bits are set. This means the write operation ended with CRC error. See
Table 28-14
registers in the SDHC.
Freescale Semiconductor
BUF_WRITE_EN Bus Write Enable. This bit controls the buffer write ready interrupt. If this bit is 1, interrupt is enabled. When
END_CMD_RES End Command Response. This bit controls the interrupt generation on the status at the end of the command
SDHC_STATUS Bit
WRITE_CRC_ERR No, alert using the
TIME_OUT_READ
TIME_OUT_RESP
READ_CRC_ERR
RESP_CRC_ERR
WRITE_OP_
READ_OP_
DONE
DONE
Field
Source:
for a summary of the relationship between the interrupt, interrupt control register, and status
the buffer becomes empty during a write operation, an interrupt is generated. Write data to the FIFO and clear
the STATUS[BUF_WR_RDY] bit to clear the interrupt.
0 Buffer status interrupt disabled.
1 Buffer status interrupt enabled.
response. When this bit is 1, the SDHC generates an interrupt at the end of the command response status.
0 End Command-response interrupt disabled.
1 End Command-response interrupt enabled.
Write Operation Done. This bit controls the interrupt generation for the status of write operation. When the
interrupt enabled, the SDHC generates an interrupt when the configured bytes of data are transferred to the
card.
0 Write_OP_DONE interrupt disabled
1 Write_OP_DONE interrupt enabled
Read Operation Done. This bit controls the interrupt generation for the status of read operation completion.
When the interrupt is enabled, the SDHC generates an interrupt when the pre-defined bytes of data are
transferred from the card.
0 READ_OP_DONE interrupt disabled
1 READ_OP_DONE interrupt enabled
No, alert using the
SDHC_STATUS[READ_OP_DONE] bit.
No, alert using the
SDHC_STATUS[END_CMD_RESP] bit.
SDHC_STATUS[WRITE_OP_DONE] bit.
No, alert using the
SDHC_STATUS[READ_OP_DONE] bit.
No, alert using the using
SDHC_STATUS[END_CMD_RESP] bit.
Table 28-13. SDHC_INT_CNTR field descriptions (continued)
directly generate interrupt?
MPC5125 Microcontroller Reference Manual, Rev. 2
Does status
Table 28-14. Interrupt Mechanisms
Description
SDHC_INT_CNTR Bit
WRITE_OP_DONE
READ_OP_DONE
READ_OP_DONE
END_CMD_RES
END_CMD_RES
Secure Digital Host Controller (SDHC)
Clear status by writing 1
Clear status by writing 1
Clear status by writing 1
Clear status by writing 1
Clear status by writing 1
Interrupt/Status
Clear Method
28-19