MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 662

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

NAND Flash Controller (NFC)
4
In case flash devices are used with a physical page size of 4 KB or more, the bad block marker will appear
as the first byte of the spare area, but because of the physical-to-virtual mapping, it will not appear in byte
2048 of the virtual page, where its logical place would be. The DMA engine contains the option to swap
some bytes, and in order to make the bad block marker appear in the requested place.
1
23.8.6
There is a sequencer inside cmd_block. Sequencer state variable is flash_req_phase[15:0], which is
preloaded from FLASH_CMD_CODE. Each bit of flash_req_phase stands for a certain action. If the bit
is set, the action is executed. If the bit is cleared, the action is not executed. flash_req_phase is preloaded
from FLASH_CMD_CODE. When command repeat is enabled, the preload takes place for every tick of
repeat count. There is additional code to control the reloading.
23-32
Flash sector size
Flash_req_
phase bit
When a 4 KB page is split to eight virtual pages, if page program/read using DMA, set PAGE_CNT = 8, if not using DMA, set
PAGE_CNT = 4. See
Only works with a user page size of at least 2055 bytes. Does not work with ECC mode 111.
(main + spare)
4096 + 128
4096 + 208
15
14
13
12
11
10
9
8
7
6
bytes
Table 23-21. Use of swap field to get bad block marker in position 2048 with large page flash
Flash Command Sequencer
Start DMA transfer to read data from memory , and write to SRAM.
Sent Command byte 1 to flash. See FLASH_CMD_BYTE1,
(FLASH_CMD2).”
Sent column address 1 to flash. See COL_ADDR1,
Sent column address 2 to flash. See COL_ADDR2,
Sent row address 1 to flash. See ROW_ADDR1,
Sent row address 2 to flash. See ROW_ADDR2,
Sent row address 3 to flash. See ROW_ADDR3,
Write data to flash. Total of PAGE_CNT (see
pages is written to the flash, and equal number of starts is sent to the residue engine. Also, additional starts to
the DMA engine are sent, until DMA has transferred all the PAGE_CNT data from memory to NFC.
Sent Command byte 2 to flash. See FLASH_CMD_BYTE2,
(FLASH_CMD1).”
Wait for flash R/B handshake.
4096
4096
Bad block
(physical)
Section 23.8.2.1, “Page Read,”
marker
MPC5125 Microcontroller Reference Manual, Rev. 2
Page 1/byte 1984 Page 1/byte 2048
Page 1/byte 1944 Page 1/byte 2048
Table 23-22. Detail of flash_req_phase
before swap
Bad block
(virtual)
marker
and
Action when bit is set
Section 23.7.13, “Flash Configuration register
Section 23.8.2.2, “Page Program,”
After swap
(expected)
Bad block
marker
Section 23.7.4, “Row Address register (ROW_ADDR).”
Section 23.7.4, “Row Address register (ROW_ADDR).”
Section 23.7.4, “Row Address register (ROW_ADDR).”
Section 23.7.3, “Column Address register (COL_ADDR).”
Section 23.7.3, “Column Address register (COL_ADDR).”
Section 23.7.2, “Flash Command 2 register
Section 23.7.1, “Flash Command 1 register
CACHE_SWAP_ADDR1[13:3] = (1984/8)
CACHE_SWAP_ADDR2[13:3] = (2048/8)
CACHE_SWAP_ADDR1[13:3] = (1944/8)
CACHE_SWAP_ADDR2[13:3] = (2048/8)
for more details.
Swap
Freescale Semiconductor
(FLASH_CONFIG)”)
1