MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet

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MPC5125 Microcontroller Reference Manual Devices Supported: MPC5125 Document Number: MPC5125RM Rev. 2 11/2009 ...

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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...

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... Local Access Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.2.6 Overlap of Local Access Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.2.7 Configuring Local Access Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3 System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.1 System Configuration Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 1 Overview 1-5 Chapter 2 (XLBMEN + Mem Map) ...

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... PSC Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.2.4 MSCAN Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.5 OUT Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.6 RTC Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2.7 System PLL lock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5 MPC5125 Microcontroller Reference Manual, Rev Chapter 3 Signal Descriptions Chapter 4 Reset Chapter 5 Clocks and Low-Power Modes Freescale Semiconductor ...

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... CSB Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.2.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.3.1 Arbitration Policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 6 Chapter 7 Chapter 8 CSB Arbiter and Bus Monitor v ...

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... Gamma Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-37 10.4.8 Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-38 10.4.9 Writeback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-40 10.4.10Color Bar Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-41 10.4.11Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-41 10.4.12Dynamic Priority Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-42 10.4.13Display Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-43 MPC5125 Microcontroller Reference Manual, Rev Chapter 9 Direct Memory Access (DMA) Chapter 10 Display Interface Unit (DIU) Freescale Semiconductor ...

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... Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-19 12.4.3 Congestion Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-21 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2.1 EMB Mux . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 11 DRAM Controller Chapter 12 Chapter 13 External Memory Bus (EMB) vii ...

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... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-2 15.2.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.3.1 Input Capture Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-10 15.3.2 Changing Sub-Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-11 15.3.3 Output Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-12 MPC5125 Microcontroller Reference Manual, Rev. 2 viii Chapter 14 Fast Ethernet Controller (FEC) Chapter 15 General Purpose Timers (GPT) Freescale Semiconductor ...

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... Mixed Interrupts Group Relative Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-39 18.3.5 Highest Priority Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-39 18.3.6 Interrupt Source Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-39 18.3.7 Masking Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-43 18.3.8 Interrupt Vector Generation and Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-44 MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 16 General Purpose I/O (GPIO) Chapter 17 IIM/Fusebox Chapter 18 ...

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... Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.2.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-4 21.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22 21.3.1 Non-Muxed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-22 21.3.2 Muxed Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-30 21.3.3 SCLPC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-37 21.3.4 Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-38 MPC5125 Microcontroller Reference Manual, Rev Chapter 19 Inter-Integrated Circuit (I Chapter 20 I/O Control Chapter Freescale Semiconductor ...

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... Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-4 23.6.2 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.7 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 23.7.1 Flash Command 1 register (FLASH_CMD1 23-8 23.7.2 Flash Command 2 register (FLASH_CMD2 23-8 23.7.3 Column Address register (COL_ADDR 23-9 MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 22 MSCAN Chapter 23 NAND Flash Controller (NFC) xi ...

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... PRE_DIV Copy Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.3.8 Low-Power Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 Programmable Serial Controller (PSC) 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.3 PSC Functions Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.4 Memory Map and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.4.1 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-6 MPC5125 Microcontroller Reference Manual, Rev. 2 xii Chapter 24 Chapter 25 Freescale Semiconductor ...

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... Detailed Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.3 Memory Map and Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.3.1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.3.2 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-23 28.4.1 Data Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-23 MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Chapter 26 Chapter 27 Real Time Clock (RTC) Chapter 28 xiii ...

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... Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.2 Memory Map/Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-2 32.2.1 Module Identification Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-7 32.2.2 Capability Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-12 32.2.3 Device/Host Timer Registers (Non-EHCI 32-16 MPC5125 Microcontroller Reference Manual, Rev. 2 xiv Chapter 29 Chapter 30 SRAM Memory (MEM) Chapter 31 Temperature Sensor Chapter 32 Freescale Semiconductor ...

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... Device Operational Model For Packet Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-159 32.8.6 Managing Queue Heads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-167 32.8.7 Managing Transfers with Transfer Descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-169 32.8.8 Device Error Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-171 32.8.9 Servicing Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-172 32.8.10Deviations from the EHCI Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-173 MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor xv ...

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... A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 A.2 MPC5125 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-1 MPC5125 Microcontroller Reference Manual, Rev. 2 xvi Appendix A Memory Map Freescale Semiconductor ...

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... Chapter 8, “CSB Arbiter and Bus Monitor,” its configuration, control, and status registers. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor includes general descriptions of the modules and features incorporated in summarizes the external signal functions, their static electrical describes the various clock sources that are available ...

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... UART, AC97, Codec, and I describes the real time clock. describes the counter that guards against describes the priority manager for summarizes the software and module, including I C protocol, describes the power blocks that describes the centralized FIFO describes the module that interfaces to Freescale Semiconductor 2 S ...

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... Product briefs—Each device has a product brief that provides an overview of its features. This document is roughly equivalent to the overview (Chapter device’s reference manual. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor describes the on-chip static RAM (SRAM) describes the module that monitors the internal temperature of provides a detailed listing of the memory-mapped registers for the ...

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... Application notes—These short documents address specific design issues useful to programmers and engineers working with Freescale Semiconductor processors. Additional literature is published as new processors become available. For a current list of PowerPC documentation, refer to http://www.freescale.com/powerarchitecture Conventions This document uses the following notational conventions: cleared/set When a bit takes the value zero said to be cleared ...

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... R FIELDNAME Write 1 to clear: indicates that writing this bit field clears it. W w1c R FIELDNAME Read to clear: indicates that reading this bit field clears it, regardless of its returned value. W r1c R 0 Indicates a self-clearing bit. W FIELDNAME MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor xxi ...

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... Least-significant bit MAC Multiply accumulate unit, also Media access controller MSB Most-significant byte msb Most-significant bit Mux Multiplex NOP No operation OEP Operand execution pipeline PC Program counter MPC5125 Microcontroller Reference Manual, Rev. 2 xxii Table i. Acronyms and Abbreviated Terms Meaning Freescale Semiconductor ...

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... Phase-locked loop POR Power-on reset RISC Reduced instruction set computing Rx Receive SOF Start of frame TAP Test access port TTL Transistor transistor logic Tx Transmit UART Universal asynchronous/synchronous receiver transmitter USB Universal serial bus MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Meaning xxiii ...

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... Signal displacement value, n bits wide (example: d16 is a 16-bit displacement) SF Scale factor (x1, x2, x4 for indexed addressing mode, <<1n>> for MAC operations) MPC5125 Microcontroller Reference Manual, Rev. 2 xxiv Table ii. Notational Conventions Operand Syntax Opcode Wildcard Register Specifications Miscellaneous Operands Freescale Semiconductor ...

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... Least significant bit (example: lsb of D0) LSB Least significant byte LSW Least significant word msb Most significant bit MSB Most significant byte MSW Most significant word MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Operand Syntax Operations Subfields and Qualifiers is a 16-bit displacement) 16 xxv ...

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... Table iii. MPC5125 Microcontroller Reference Manual Revision History Revision Revision Number Date 1 06/2008 Release 1 of this document. 2 7/2009 Release 2 of this document. Significant technical and editorial revision. MPC5125 Microcontroller Reference Manual, Rev. 2 xxvi Description of Changes Freescale Semiconductor ...

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... The performance of the MPC5125 is enhanced by having well-balanced system resources for the integrated core, graphics and audio engines, DDR1/DDR2/SDR/Mobile DDR memory controllers and integrated 64-channel DMA support. Figure 1-1 shows a top-level block diagram of the MPC5125. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 1-1 ...

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... MPC5125 Microcontroller Reference Manual, Rev. 2 1-2 Display SDR, Mobile DDR, DDR1/2 Memory DIU Multi-Port Memory Controller 32 KB SRAM MPC5125 e300 Power Architecture 32 KB instruction / 32 KB data cache Figure 1-1. MPC5125 Block Diagram FEC1 FEC2 USB1 ULPI USB2 ULPI DMA 64-Channel Freescale Semiconductor ...

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... Both USB controllers can be accessed through the ULPI interface 1.3.4 Direct Memory Access (DMA) Controller • 64-channel on-chip DMA engine with advanced capabilities • Supports channel linking and scatter/gather processing MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Freescale Confidential Proprietary, NDA Required 2 C) communication interfaces Overview 1-3 ...

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... Supports as many as 42-bit non-muxed interfaces • Supports large-packet DMA transfers 1.3.10 Secure Digital Host Controller (SDHC) • Two SD/SDIO/MMC card interfaces • Compliant with SD and SDIO specification version 1.x • Compliant with MMC card specification MPC5125 Microcontroller Reference Manual, Rev. 2 1-4 Freescale Semiconductor ...

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... On-chip Real-time Clock (RTC) • Real-time clock runs from separate V • Programmable alarm • Periodic interrupts for one second, one minute, one day MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Freescale Confidential Proprietary, NDA Required communication interfaces 2 S) power domain available for external wake up (GPIO1) ...

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... Evaluation/development boards • IDE/tool chains • C/C++ compilers • Hardware and software debuggers • Initialization/boot code generators • Software libraries • Device/module drivers • JTAG interfaces • Third party real-time operating systems (RTOS) MPC5125 Microcontroller Reference Manual, Rev. 2 1-6 Freescale Semiconductor ...

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... MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Freescale Confidential Proprietary, NDA Required Overview 1-7 ...

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... Overview MPC5125 Microcontroller Reference Manual, Rev. 2 1-8 Freescale Semiconductor ...

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... KB; however, a 256 KB memory window is reserved for SRAM. Window 12 is used for the NAND Flash Controller. The NAND Flash Controller base address register is located at IMMR + 0xC8. The block size is fixed at 1 MB. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2-1. The registers that set the base address and size of each local access 2-2. Table 2-1 ...

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... MPC5125 Microcontroller Reference Manual, Rev. 2 2-2 NOTE NOTE Target Interface MB. There is no attributes register associated Comments Fixed 1 MB window size — — — — — — — — — — — Fixed 256 KB window size Fixed 1 MB window size Freescale Semiconductor ...

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... Table 2-4 for individual module base addresses. 0x004–0x01F Reserved MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor System Configuration and Memory Map (XLBMEN + Mem Map) Section 2.2.5.1.1, “Internal Memory NOTE Section 2.2.1, “Local Memory Map Overview and A detailed description of the local access ...

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... Base address and size set by the START_ADDR and STOP_ADDR fields of the LPCS7AW register. MPC5125 Microcontroller Reference Manual, Rev. 2 2-4 Register 1 Access Reset Value Section/Page 2 R/W U 2.2.5.1.3/2-8 R/W 2.2.5.1.3/2-8 R/W 2.2.5.1.3/2-8 R/W 2.2.5.1.3/2-8 R/W 2.2.5.1.3/2-8 R/W 2.2.5.1.3/2-8 R/W 2.2.5.1.3/2-8 R/W 2.2.5.1.3/2-8 R/W 2.2.5.1.3/2-8 Freescale Semiconductor ...

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... The effect of the update must be guaranteed to be visible by the mapping logic before an access to the new location is accessed. To make sure this happens, these guidelines should be followed: MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor System Configuration and Memory Map (XLBMEN + Mem Map) Register Table 2-4 ...

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... Integrated programmable interrupt controller (IPIC) CSB arbiter Reset module (RESET) Clock module (CLOCK) Power management control (PMC) Figure 2-1. Access: User read/write Section/Page Chapter 2/2-1 Chapter 29/29-1 Chapter 27/27-1 Chapter 15/15-1 Chapter 18/18-1 Chapter 8/8-1 Chapter 4/4-1 Chapter 5/5-1 Chapter 24/24-1 Freescale Semiconductor ...

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... MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor System Configuration and Memory Map (XLBMEN + Mem Map) 1 Region Name General Purpose I/O (GPIO1) General Purpose I/O (GPIO2) Reserved MSCAN1 MSCAN2 Byte data link controller (BDLC) ...

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... STOP_ADDR See Table 2-6 Section/Page Chapter 21/21-1 Chapter 25/25-1 Chapter 25/25-1 Chapter 25/25-1 Chapter 25/25-1 Chapter 25/25-1 Chapter 25/25-1 Chapter 25/25-1 Chapter 25/25-1 Chapter 25/25-1 Chapter 25/25-1 Chapter 25/25-1 Chapter 9/9-1 2-2. Access: User read/write Table 2-6. Freescale Semiconductor 15 31 ...

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... Figure 2-8. 2.2.5.1.4 LocalPlus CS0–7 Access Window Registers (LPCSxAW) The LocalPlus Access Window Registers (LPCSxAW) are shown in MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor System Configuration and Memory Map (XLBMEN + Mem Map) Table 2-5. LPBAW field descriptions Description START_ADDR BMS ...

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... Base + 0x0034 (LPCS4AW) Base + 0x0038 (LPCS5AW) Base + 0x003C (LPCS6AW) Base + 0x0040 (LPCS7AW START_ADDR See Table 2 STOP_ADDR See Table 2-6 Table 2-7. LPCSxAW field descriptions Description BASE_ADDR Table 2-8. DDRLAWBAR0 field descriptions Description Access: User read/write Access: User read/write Freescale Semiconductor ...

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... SRAM Base Address Register (SRAMBAR) Figure 2-6 shows the SRAM Base Address Register (SRAMBAR). Address: Base + 0x00C4 Reset Reset Figure 2-6. SRAM Base Address Register (SRAMBAR) MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor System Configuration and Memory Map (XLBMEN + Mem Map Table 2-9 ...

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... BMS and ROM_LOC fields. Table 2-12 defines the reset value NFCBAR[BASE_ADDR]. MPC5125 Microcontroller Reference Manual, Rev. 2 2-12 Table 2-10. SRAMBAR field descriptions Description NOTE Section 2.2.5.1.9, “NFCBAR[BASE_ADDR] Reset Value,” BASE_ADDR See Table 2- Table 2-11. NFCBAR field descriptions Description Access: User read/write Freescale Semiconductor ...

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... MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor System Configuration and Memory Map (XLBMEN + Mem Map) BASE_ADDR BMS Reset Value 0 0x000 1 0xFFF x 0x400 NOTE BOOT_STOP NFC_BASE_ADDR 0x007F FFFF ...

Page 48

... Some general information and configuration options that affect the system behavior and performance are described in the following sections. MPC5125 Microcontroller Reference Manual, Rev. 2 2-14 NAND FLASH LPC BOOT ROM NAND FLASH LPC BOOT ROM ROM_LOC = 00 ROM_LOC = x1 BMS = 1 BMS = 0 LPC BOOT ROM LPC BOOT ROM NAND FLASH NAND FLASH ROM_LOC = x1 ROM_LOC = x0 BMS = 1 BMS = x Freescale Semiconductor ...

Page 49

... PARTID field intended to help factory test and user code which is sensitive to part changes. The mask number changes with each mask set change. PARTID and REVID are specific for the e300 SVR value. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor System Configuration and Memory Map (XLBMEN + Mem Map) Register Figure 2-9 ...

Page 50

... NFC boot after soft reset if ROM_LOC = 01. Temperature Sensor TEMPPD 0 Temperature Sensor is enabled. 1 Temperature Sensor is disabled. MPC5125 Microcontroller Reference Manual, Rev. 2 2-16 Figure 2- TBEN Table 2-16. SPCR field descriptions Description controls the priority of requests for Access: User read/write COREPR NFCB TEMP OOT TEMPSEL Freescale Semiconductor ...

Page 51

... Field TEMPSEL Temperature Sensor select trip point 000 105 °C 001 95 °C 010 85 °C 011 75 °C 100 65 °C 101 55 °C 110 45 °C 111 35 °C MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor System Configuration and Memory Map (XLBMEN + Mem Map) Description 2-17 ...

Page 52

... System Configuration and Memory Map (XLBMEN + Mem Map) MPC5125 Microcontroller Reference Manual, Rev. 2 2-18 Freescale Semiconductor ...

Page 53

... Individual chapters of this document provide details for each signal, describing each signal’s behavior when asserted and negated and when the signal is an input or an output. Power signals are described in the MPC5125 Microcontroller Data Sheet. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE • USB ULPI interface signals • ...

Page 54

... TDO 1 TMS 1 TRST 1 PORESET 1 HRESET 1 SRESET 1 SYS_XTALO 1 SYS_XTALI 1 RTC_XTALO 1 RTC_XTAL1 1 HIB_MODE 1 TEST 1 GPIO[3:0] 4 Freescale Semiconductor NFC Interface 2 Signals LPC Interface 9 Signals EMB Interface 32 Signals USB Interface 12 Signals SDHC Interface 6 Signals JTAG 5 Signals System Control 3 Signals System Clock Interface 2 Signals RTC Interface ...

Page 55

Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset GPIO00 — ALT0 GPIO00 ALT1 — ALT2 — ALT3 — GPIO01 — ALT0 GPIO01 ALT1 — ALT2 — ALT3 — GPIO02 — ALT0 GPIO02 ALT1 — ALT2 — ...

Page 56

Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset TMPS_ANAVI — ALT0 TMPS_ANAVIZ Z ALT1 — ALT2 — ALT3 — SYS_XTALI — ALT0 SYS_XTALI ALT1 — ALT2 — ALT3 — SYS_XTALO — ALT0 SYS_XTALO ALT1 — ALT2 ...

Page 57

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MVTT1 — ALT0 MVTT1 ALT1 — ALT2 — ALT3 — MVTT2 — ALT0 MVTT2 ALT1 — ALT2 — ALT3 — MVTT3 — ...

Page 58

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ04 0x00 ALT0 MDQ04 IO_CON- ALT1 — TROL_MEM ALT2 — ALT3 — MDQ05 0x00 ALT0 MDQ05 IO_CON- ALT1 — TROL_MEM ALT2 — ...

Page 59

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ12 0x00 ALT0 MDQ12 IO_CON- ALT1 — TROL_MEM ALT2 — ALT3 — MDQ13 0x00 ALT0 MDQ13 IO_CON- ALT1 — TROL_MEM ALT2 — ...

Page 60

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ20 0x00 ALT0 MDQ20 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 GPT1[4] MDQ21 0x00 ALT0 MDQ21 ALT1 — IO_CON- ALT2 — TROL_MEM ...

Page 61

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQ28 0x00 ALT0 MDQ28 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 GPIO25 MDQ29 0x00 ALT0 MDQ29 ALT1 — IO_CON- ALT2 — TROL_MEM ...

Page 62

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MDQS0 0x00 ALT0 MDQS0 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MDQS1 0x00 ALT0 MDQS1 ALT1 — IO_CON- ALT2 — TROL_MEM ...

Page 63

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MA01 0x00 ALT0 MA01 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MA02 0x00 ALT0 MA02 ALT1 — IO_CON- ALT2 — TROL_MEM ...

Page 64

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MA09 0x00 ALT0 MA09 ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MA10 0x00 ALT0 MA10 ALT1 — IO_CON- ALT2 — TROL_MEM ...

Page 65

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset MCK 0x00 ALT0 MCK ALT1 — IO_CON- ALT2 — TROL_MEM ALT3 — MCKE 0x00 ALT0 MCKE ALT1 — IO_CON- ALT2 — TROL_MEM ...

Page 66

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset LPC_AX03 0x09 ALT0 LPC_AX03/LPC_TS ALT1 NFC_CE2 STD_PU ALT2 LPC_CS2 ALT3 — EMB_AD00 0x2C ALT0 LPC_AD00/NFC_AD00 ALT1 — STD_PU ALT2 RST_CONF_LOC0 ALT3 — ...

Page 67

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD07 0x25 ALT0 LPC_AD07/NFC_AD07 ALT1 — STD_PU ALT2 RST_CONF_COREPLL4 ALT3 — EMB_AD08 0x24 ALT0 LPC_AD08/NFC_AD08 ALT1 PSC3_2 STD_PU ALT2 RST_CONF_SPMF0 ALT3 GPIO28 ...

Page 68

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD15 0x1D ALT0 LPC_AD15/NFC_AD15 ALT1 PSC2_0 STD_PU ALT2 RST_CONF_SYSOSCEN ALT3 GPIO21 EMB_AD16 0x1C ALT0 LPC_AD16/LPC_A01/NFC_WE ALT1 — STD_PU ALT2 — ALT3 — ...

Page 69

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD23 0x15 ALT0 LPC_AD23/LPC_A08 ALT1 — STD_PU ALT2 — ALT3 GPIO17 EMB_AD24 0x14 ALT0 LPC_AD24/LPC_A09 ALT1 — STD_PU ALT2 — ALT3 GPIO16 ...

Page 70

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset EMB_AD31 0x0D ALT0 LPC_AD31/LPC_A16 ALT1 PSC_MCLK_IN STD_PU_S ALT2 — T ALT3 GPIO09 EMB_AX00 0x0C ALT0 LPC_AX00/LPC_ALE ALT1 — STD_PU ALT2 — ALT3 ...

Page 71

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_HSYNC 0x031 ALT0 DIU_HSYNC ALT1 PSC4_2 STD_PU ALT2 USB1_DATA2 ALT3 LPC_AX06 DIU_VSYNC 0x032 ALT0 DIU_VSYNC ALT1 PSC4_3 STD_PU ALT2 USB1_DATA3 ALT3 GPIO31 ...

Page 72

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_LD06 0x039 ALT0 DIU_LD06 ALT1 PSC5_3 STD_PU ALT2 USB1_STOP ALT3 GPIO35 DIU_LD07 0x03A ALT0 DIU_LD07 ALT1 PSC5_4 STD_PU_S ALT2 USB1_CLK T ALT3 ...

Page 73

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_LD14 0x041 ALT0 DIU_LD14 ALT1 PSC7_1 STD_PU ALT2 USB2_DATA2 ALT3 GPT2[2] DIU_LD15 0x042 ALT0 DIU_LD15 ALT1 PSC7_2 STD_PU ALT2 USB2_DATA3 ALT3 GPT2[3] ...

Page 74

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset DIU_LD22 0x049 ALT0 DIU_LD22 ALT1 PSC8_2 STD_PU ALT2 USB2_DIR ALT3 GPIO43 DIU_LD23 0x04A ALT0 DIU_LD23 ALT1 PSC8_3 STD_PU ALT2 USB2_NEXT ALT3 GPIO44 ...

Page 75

Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset CAN1_TX 0x4D ALT0 CAN1_TX ALT1 PSC9_0 STD_PU_S ALT2 I2C2_SCL T ALT3 GPIO47 CAN2_TX 0x4E ALT0 CAN2_TX ALT1 PSC9_1 STD_PU_S ALT2 I2C2_SDA T ALT3 GPIO48 FEC1_TXD_2 0x51 ALT0 FEC1_TXD_2 ...

Page 76

Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset FEC1_RXD_1 0x57 ALT0 FEC1_RXD_1/RMII_RX1 ALT1 PSC3_1 STD_PU ALT2 USB2_DATA6 ALT3 GPIO57 FEC1_TXD_1 0x58 ALT0 FEC1_TXD_1/RMII_TX1 ALT1 PSC3_2 STD_PU ALT2 USB2_DATA7 ALT3 GPIO58 FEC1_MDC 0x59 ALT0 FEC1_MDC/RMII_MDC ALT1 PSC3_3 ...

Page 77

Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset FEC1_RX_CL 0x5F ALT0 FEC1_RX_CLK K ALT1 PSC0_1 STD_PU_S ALT2 NFC_R/B2 T ALT3 GPIO05 FEC1_RX_DV 0x60 ALT0 FEC1_RX_DV/RMII_CRS_DV ALT1 PSC0_2 STD_PU_S ALT2 NFC_R/B3 T ALT3 GPIO06 FEC1_TX_EN 0x61 ALT0 ...

Page 78

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset USB1_DATA4 0x67 ALT0 USB1_DATA4 ALT1 PSC1_4 STD_PU ALT2 FEC2_MDIO/RMII_MDIO ALT3 — USB1_DATA5 0x68 ALT0 USB1_DATA5 ALT1 PSC4_0 STD_PU ALT2 FEC2_RXD_0/RMII_RX0 ALT3 — ...

Page 79

Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset SDHC1_CLK 0x6F ALT0 SDHC1_CLK ALT1 NFC_CE1 STD_PU ALT2 FEC2_TXD_2 ALT3 GPIO11 SDHC1_CMD 0x70 ALT0 SDHC1_CMD ALT1 PSC5_0 STD_PU ALT2 FEC2_TXD_3 ALT3 GPIO12 SDHC1_D0 0x71 ALT0 SDHC1_D0 ALT1 PSC5_1 ...

Page 80

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset PSC0_1 0x77 ALT0 PSC0_1 ALT1 SDHC2_D0 STD_PU ALT2 GPT1[1] ALT3 GPIO16 PSC0_2 0x78 ALT0 PSC0_2 ALT1 SDHC2_D1_IRQ STD_PU ALT2 GPT1[2] ALT3 GPIO17 ...

Page 81

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset PSC1_4 0x7F ALT0 PSC1_4 ALT1 CKSTP_OUT STD_PU ALT2 NFC_CE2 ALT3 GPIO20 J1850_TX 0x80 ALT0 J1850_TX ALT1 — STD_PU_S ALT2 NFC_CE3 T ALT3 ...

Page 82

Table 3-1. MPC5125 Pin Multiplexing (continued) Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset HRESET — ALT0 HRESET ALT1 — ALT2 — ALT3 — PORESET — ALT0 PORESET ALT1 — ALT2 — ALT3 — SRESET — ...

Page 83

Pad I/O Control Alternate Pin 1 3 Register Function 2 and Offset TEST — ALT0 TEST ALT1 — ALT2 — ALT3 — 1 Pins controlled by the STD_PU_ST register have a Schmitt trigger input; pins controlled by the STD_PU register ...

Page 84

... Table 3-3 Signal Table 3-2) shows states of the State During Reset 1 All 0 16’h8000 Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Freescale Semiconductor ...

Page 85

... NFC Chip Enable 0 DIU_LD00 CAN3_RX DIU_LD01 CAN3_TX DIU_LD08 CAN4_RX DIU_LD09 CAN4_TX DIU_LD16 I2C3_SCL MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Signal Signal Signal Descriptions State During Reset Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor ...

Page 86

... Signal Chapter 20, “IO Control.” State During Reset Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Pullup resistor Z Freescale Semiconductor ...

Page 87

... The JTAG initiated reset (power on reset, hardware reset, and soft reset) is independent of the reset state of the JTAG controller (TRST) 2. The Reset Control Register may initiate a SRESET or HRESET sequence. see MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2 HRESET Flow Figure 4-1. Internal Reset Flow Table 4-1 ...

Page 88

... MPC5125 Microcontroller Reference Manual, Rev. 2 4-2 1 HRESET — — — — — — — — — x — — — — — x — — — — — Power-On-Reset SRESET — — — x — — x — — x — — Section 4.5.3, “JTAG Reset.” Freescale Semiconductor ...

Page 89

... Checkstop may be initiated when the e300 core enters the checkstop state. This state may be masked in the RESET module, e300 core or IPIC. 2. The reset configuration register in the RESET module may initiate either a SRESET or HRESET sequence. 3. The RTC timer mechanism retains state as long as V MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 2 3 provides power to the RTC module bat ...

Page 90

... RCWLR and RCWHR registers (see Available modes include: • Test modes • Boot interface selection MPC5125 Microcontroller Reference Manual, Rev. 2 4-4 power domain (see Section 4.5.2, “RTC at BAT Reset”) Section 4.6, “Memory Map”). Freescale Semiconductor ...

Page 91

... Only valid when LPC boot mode is selected (ROM_LOC). 2 NFC memory access windows are placed at the location indicated by the BMS bit. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 4-2. Reset Configuration Word Boot mode select — Selects e300 boot vector for LPC CS0 or NFC base address. See Selects boot device ...

Page 92

... BAT ns must be tied to a defined state or undefined behavior may Section 4.5, “Reset Configuration Word for details. Each interface requires a unique boot strap BMS = 1 (boot high) 0xFFF0_0100 BMS = 1 (boot high) 0xFF80_0000 0xFFFF_FFFF 0xFFF0_0000 . BAT (RST_CONF)”). These pins Freescale Semiconductor ...

Page 93

... Configure IMMR 2 Configure DRAM & NFC Clock Dividers 3 Configure NFC parameters MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 4-5. LPC Initialization Sequence Software Region Reset Vector (Flash) Reset Vector (Flash) Reset Vector (Flash) Reset Vector (Flash) Relative branching should not be used ...

Page 94

... Perform any initialization required by monitor or RTOS here. (DRAM) Start Application Environment (RTOS) Table 4-7. Register Note — — — 2 Access Reset Value Section/Page R 0x0U0U_0U00 4.6.1/4-9 R 0xUUU0_UU00 4.6.2/4-9 R/W 0x6000_0000 4.6.3/4-10 R/W 0x0000_0000 4.6.4/4-12 R/W 0x0000_0000 4.6.5/4-13 R/W 0x0000_0000 4.6.6/4-13 R/W 0x0000_0000 4.6.7/4-14 Freescale Semiconductor ...

Page 95

... System clock divide factor. See 4.6.2 Reset Configuration Word High (RCWH) Register The Reset Configuration Word High register is shown in according to the reset configuration word high loaded during the reset flow. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 4-2. This read-only register gets its value ...

Page 96

... LPC_ LPC_ LPC_DBW EMB_ EMB_ EMB_ EMB_ AD18 AD19 AD04 AD03 Table 4-9. RCWH field descriptions Description NOTE Figure 4-4 captures various reset events in the device. Access: User read-only ROM_LOC EMB_ EMB_ AD01 AD00 Section 4.5.1, “BMS Operation.” Freescale Semiconductor ...

Page 97

... Software watchdog reset status. When a software watchdog expire event (which causes a reset) is detected, the SWRS bit is set and remains that way until the software clears it. SWRS is cleared by writing a logic software watchdog reset event occurred software watchdog reset event has occurred. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ...

Page 98

... Reset generated when the system PLL unlocks. MPC5125 Microcontroller Reference Manual, Rev. 2 4-12 Description NOTE Figure 4-5, controls the internal reset sources Figure 4-5. Reset Mode Register (RMR) Table 4-11. RMR field descriptions Description Access: User read/write PURE CSRE KILL Freescale Semiconductor ...

Page 99

... The Reset Control Register (RCR) shown in reset sequence. To allow writing to this register, the user must first write the value 0x5253_5445 to the Reset Protection Register (RPR). MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Figure 4-6, enables or disables writing to the Reset Control ...

Page 100

... MPC5125 Microcontroller Reference Manual, Rev Figure 4-7. Reset Control Register (RCR) Table 4-13. RCR field descriptions Description Figure 4-8, indicates by the CRE field that the Reset Table 4-14. RCER field descriptions Description Access: User read/write Access: User read/write Freescale Semiconductor CRE 0 ...

Page 101

... XTALI REF_CLK SPLL_OUT SYS SYS_ PLL OSC XTALO SPMF[3:0] RST_CONF_SYSOSCEN MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Section 4.2, “(PORESET) Power-On Initialization.” SYS_CLK SYS_DIV SYSDIV[5:0] 1/2 Power Arch. Figure 5-1. MPC5125 Clock System DDR ddr_clk 1/2 Memory Device ...

Page 102

... REF_CLK csb_clk Model”) Model”) Definition”) Definition”) Definition”) Definition”) Definition”) Definition”) 5-3. 5-4. Freescale Semiconductor ...

Page 103

... This circuit is replicated for each PSC and can be controlled by accessing the PSC Clock Control Registers (see Section 5.3.1.8, “PSC0 Clock Control Register (P0CCR),” 1. PSC_MCLK_IN and CAN_CLK_IN are generated by external pins. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Reference Clock 2 ips_clk ips_clk, rtc_clk ...

Page 104

... PSC_MCLK_IN and CAN_CLK_IN are generated by external pins. MPC5125 Microcontroller Reference Manual, Rev. 2 5-4 MSCAN_EN mscan_src Clock divider Gate IP clock CLKSRC (from MSCAN module) Out_CLK_EN Clock mclk_div Gate Out_CLK_SRC Figure 5-4. Out Clock Generation CAN_SOURCE_CLK 1 Out_CLK_OUT voltage domain circuitry BAT Freescale Semiconductor ...

Page 105

... Section 5.3.1.28, “System PLL Lock Counter Register (SPLL_LOCK_CNT).” 5.2.8 System PLL and e300 PLL 5.2.8.1 System PLL Programming Model The output of the system PLL conforms to the following equation: MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor MPC5125 RTC Module V Domain V CORE ...

Page 106

... Value (Binary) 00x Core PLL BYPASS / OFF 010 011 100 101 110 111 Table 5- spll ref_clk 68:1 1 PLL BYPASS 12:1 16:1 20:1 24:1 28:1 32:1 36:1 40:1 44:1 48:1 52:1 56:1 60:1 64 cpll csb_clk 1.0: 1 1.5: 1 2.0: 1 2.5: 1 3.0: 1 3.5: 1 Freescale Semiconductor ...

Page 107

... OUT CLK2 Clock Configure Register (OUT2CCR) 0x7C OUT CLK3 Clock Configure Register (OUT3CCR) 0x80 System Clock Frequency Register 3 (SCFR3) 0x84–0x8F Reserved MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Register Access Clocks and Low-Power Modes 2 Reset Value Section/Page R 0x0U0U_0000 5.3.1.1/5-8 ...

Page 108

... The reset value is defined by the latched reset configuration word (RST_CONF). See MPC5125 Microcontroller Reference Manual, Rev. 2 5-8 Register SPMF — — — — Access Reset Value Section/Page R 0x000U_UUUU 5.3.1.28/5-35 Chapter 2, “System Configuration and Memory Access: User read/write CPMF — — — Table 4-2. Freescale Semiconductor — ...

Page 109

... Figure 5-7. System Clock Control Register 1 (SCCR1) 1 Bit is reserved, and must not be written or cleared. Value must remain 1. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 5-6. SPMR field descriptions Description Section 5.2.8.1, “System PLL Programming Model,” on page SPMF spll ref_clk ...

Page 110

... PSC5 Clock Enable 0 Disable 1 Enable PSC6_EN PSC6 Clock Enable 0 Disable 1 Enable PSC7_EN PSC7 Clock Enable 0 Disable 1 Enable PSC8_EN PSC8 Clock Enable 0 Disable 1 Enable PSC9_EN PSC9 Clock Enable 0 Disable 1 Enable MPC5125 Microcontroller Reference Manual, Rev. 2 5-10 Table 5-7. SCCR1 field descriptions Description Freescale Semiconductor ...

Page 111

... The System Clock Control Register 2 (SCCR2), shown in configurable clock ratio. Address: Base + 0x08 DIU 0 MEM USB1 _EN _EN _EN W Reset Reset Figure 5-8. System Clock Control Register 2 (SCCR2) MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Figure USB2 I2C AUTO SDHC1 _EN _EN _EN _EN ...

Page 112

... SDHC2 Clock Enable 0 Disable 1 Enable 5.3.1.4 System Clock Frequency Register 1 (SCFR1) The System Clock Frequency Register 1 (SCFR1), shown in configurable clock ratio. MPC5125 Microcontroller Reference Manual, Rev. 2 5-12 Table 5-8. SCCR2 field descriptions Description Figure 5-9, controls device units with a Freescale Semiconductor ...

Page 113

... Divide by 6. 111 Reserved. LPC_DIV LocalPlus Bus Controller (LPC) clock divide ratio 000 Reserved. 001 Divide by 1. 010 Divide by 2 (default). 011 Divide by 3. 100 Divide by 4. 101 Reserved. 110 Reserved. 111 Reserved. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor IPS_DIV 0 0 ...

Page 114

... MPC5125 Microcontroller Reference Manual, Rev. 2 5-14 Description DIV value (decimal) CSB_CLK:DIU_CLK 8 12 (default 251 62.75 252 253 63.25 254 63.5 255 63.75 Figure 5- — — 3.5 4 n/4 63 programs the SYS_DIV ratio. The Access: User read/write SDHC1_DIV Table 4-2. Freescale Semiconductor ...

Page 115

... SYS_DIV ratio. When this register gets a control signal from the Power Management Control Module (PMC) to update the main SCFR2, the value of this shadow register overwrites the SCFR2. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 5-10. SCFR2 field descriptions Description Divide Factor ...

Page 116

... Figure 5-12, provides a mechanism for retaining data after Access: User read/write Table 4-2. Divide Factor Bit Encoding 23 01_0111 24 01_1001 25 01_1010 26 01_1100 27 01_1011 28 01_1101 29 01_1110 30 10_0000 31 01_1111 32 10_0001 33 10_0010 All other settings are reserved. Freescale Semiconductor ...

Page 117

... Figure 5-13. PSC0 Clock Control Register (P0CCR) Field PSC0_ MCLK_DIV Divider Ratio MCLK_DIV mclk_out mclk_src Note: The maximum supported frequency for f A value of 0x0000 bypasses the divider. Note: This value can only be changed when the value of MCLK_EN = 0. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ...

Page 118

... MPC5125 Microcontroller Reference Manual, Rev. 2 5-18 Description Figure 5-14, controls the PSC1 MCLK divider ratio, the PSC1 PSC1_MCLK_DIV PSC1_ MCLK_ 1_SRC Table 5-14. P1CCR field descriptions Description / (MCLK_DIV + 1) is the IP Bus frequency. mclk_out Table 5-14 Access: User read/write Freescale Semiconductor defines 15 MCLK 1_EN ...

Page 119

... Note: This value can only be changed when the value of MCLK_EN equals 0. MCLK2_EN PSC2 Divider Enable 0 PSC2 divider is disabled. 1 PSC2 divider is enabled. PSC2_ PSC MCLK Divider Source MCLK_0_SRC 00 From SYS_CLK. 01 From REF_CLK. 10 From PSC_MCLK_IN. 11 From CAN_CLK_IN. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Figure 5-15, controls the PSC2 MCLK divider PSC2_MCLK_DIV ...

Page 120

... PSC MCLK Source MCLK_1_SRC 0 MCLK_DIV. 1 Reserved. MPC5125 Microcontroller Reference Manual, Rev. 2 5-20 Description Figure 5-16, controls the PSC3 MCLK divider PSC3_MCLK_DIV PSC3_ MCLK_ 1_SRC Table 5-16. P3CCR field descriptions Description / (MCLK_DIV + 1) is the IP Bus frequency. mclk_out Access: User read/write Freescale Semiconductor 15 MCLK 3_EN ...

Page 121

... The PSC5 Clock Control Register (P5CCR), shown in ratio, the PSC5 MCLK divider enable, the PSC5 MCLK divider source, and the PSC5 MCLK source. Table 5-18 defines the bit fields of P5CCR. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 5-17, controls the PSC4 MCLK divider 4 5 ...

Page 122

... P6CCR. MPC5125 Microcontroller Reference Manual, Rev PSC5_MCLK_DIV PSC5_ MCLK_ 1_SRC Table 5-18. P5CCR field descriptions Description / (MCLK_DIV + 1) is the IP Bus frequency. mclk_out Figure 5-19, controls the PSC6 MCLK divider Access: User read/write Freescale Semiconductor 15 MCLK 5_EN ...

Page 123

... PSC7 Clock Control Register (P7CCR) The PSC7 Clock Control Register (P7CCR), shown in ratio, the PSC7 MCLK divider enable, the PSC7 MCLK divider source, and the PSC7 MCLK source. Table 5-20 defines the bit fields of P7CCR. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ...

Page 124

... P8CCR. MPC5125 Microcontroller Reference Manual, Rev PSC7_MCLK_DIV PSC7_ MCLK_ 1_SRC Table 5-20. P7CCR field descriptions Description / (MCLK_DIV + 1) is the IP Bus frequency. mclk_out Figure 5-21, controls the PSC8 MCLK divider Access: User read/write Table 5-21 Freescale Semiconductor 15 MCLK 7_EN ...

Page 125

... PSC9 Clock Control Register (P9CCR) The PSC9 Clock Control Register (P9CCR), shown in ratio, PSC9 MCLK divider enable, PSC9 MCLK divider source, and the PSC9 MCLK source. Table 5-22 defines the bit fields of P9CCR. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor PSC8_MCLK_DIV ...

Page 126

... MPC5125 Microcontroller Reference Manual, Rev PSC9_MCLK_DIV PSC9_ MCLK_ 1_SRC Table 5-22. P9CCR field descriptions Description / (MCLK_DIV + 1) is the IP Bus frequency. mclk_out Figure 5-23, configures the number of Coherent Table 5-23 defines the bit fields of DCCR. Access: User read/write Freescale Semiconductor 15 MCLK 9_EN ...

Page 127

... The MSCAN1 clock control register shown in ratio, the MSCAN1 divider enable, and the MSCAN1 divider clock source. fields of M1CCR. Address: Base + 0x58 Reset MSCAN1_ CLK_SRC W Reset Figure 5-24. MSCAN1 Clock Control Register (M1CCR) MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor CLK_ INV ...

Page 128

... MPC5125 Microcontroller Reference Manual, Rev. 2 5-28 Table 5-24. M1CCR field descriptions Description / (MSCAN1_CLK_DIV + 1) mscan_src Figure 5-25 controls the MSCAN2 source clock divider MSCAN2_CLK_DIV Table 5-25. M2CCR field descriptions Description / (MSCAN2_CLK_DIV + 1) mscan_src Table 5-25 defines the bit fields Access: User read/write Freescale Semiconductor 15 MSC AN2_ ...

Page 129

... Note: This value can only be changed when the value of MSCAN3_EN equals 0. MSCAN3_EN MSCAN3 Divider Enable 0 MSCAN3 divider is disabled. 1 MSCAN3 divider is enabled. MSCAN3_ MSCAN3 CLK Source CLK_SRC 00 From SYS_CLK. 01 From REF_CLK. 10 From PSC_MCLK_IN. 11 From CAN_CLK_IN. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Figure 5-26 controls the MSCAN3 source clock divider MSCAN3_CLK_DIV ...

Page 130

... MPC5125 Microcontroller Reference Manual, Rev. 2 5-30 Figure 5-27 controls the MSCAN4 source clock divider MSCAN4_CLK_DIV Table 5-27. M4CCR field descriptions Description / (MSCAN4_CLK_DIV + 1) mscan_src Figure 5-28. Table 5-27 defines the bit Access: User read/write Table 5-28 defines the bit fields of Freescale Semiconductor 14 15 MSC AN4_ ...

Page 131

... Out Clock 1 Config Register (OUT1CCR) The Out Clock 1 clock config register is shown in OUT1CCR. Address: Base + 0x74 Reset OUT1_CLK_ 0 0 SRC W Reset Figure 5-29. Out Clock 1 Clock Config Register (OUT1CCR) MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor OUT0_DIV Table 5-28. OUT0CCR field descriptions Description / (OUT0_DIV + 1) Figure 5-29 ...

Page 132

... OUT2 divider is disabled 1 OUT2 divider is enabled MPC5125 Microcontroller Reference Manual, Rev. 2 5-32 Table 5-29. OUT1CC field descriptions Description / (OUT1_DIV + 1) Figure 5-30. Table 5- OUT2_DIV Table 5-30. OUT2CCR field descriptions Description / (OUT2_DIV + 1) defines the bit fields of Access: User read/write Freescale Semiconductor 15 OUT2 _EN ...

Page 133

... Note: This value can only be changed when the value of OUT3_EN equals 0. OUT3_EN OUT3 Divider Enable 0 OUT3 divider is disabled. 1 OUT3 divider is enabled. OUT3_CLK_SR Out Clock 3 Clock Source From SYS_CLK. 01 From REF_CLK. 10 From PSC_MCLK_IN. 11 From CAN_CLK_IN. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Figure 5-31. Table 5- OUT3_DIV 1 1 ...

Page 134

... The NFC fractional clock divider Access: User read/write NFC_RATIO_L Freescale Semiconductor ...

Page 135

... W Reset Figure 5-33. System PLL Lock Counter Register (SPLL_LOCK_CNT) 1 Reset value depends on the lock time and status of the system, and is indeterminate. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description Field value 3 0b0000_1100 (12d) 3.25 0b0000_1101 (13d) 3.5 0b0000_1110 (14d) 3.75 0b0000_1111 (15d) ...

Page 136

... The register contains the number of REF_CLK cycles between the PORESET deassertion and the System _CNT PLL lock detector indicating the first time a lock state. (SYSPLL_LOCK = 1). This bitfield is cleared by HRESET. Note: The reset value of this bitfield is indeterminate. MPC5125 Microcontroller Reference Manual, Rev. 2 5-36 Description Freescale Semiconductor ...

Page 137

... The main functional blocks of the BDLC module are explained in greater detail in the following sections. Use of the BDLC module in message networking fully implements the SAE Standard J1850 Class B Data Communication Network Interface specification. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor network. 6-1 ...

Page 138

... RX Shadow Register 8 TX Data TX Shift Register Protocol State Machine TX Data Control/ Status Symbol Encoder/Decoder TX Data J1850_TX To Physical Interface Figure 6-1. BDLC Block Diagram BARD 8 RX Data 8 RX Data RX Shift Register RX Data RX Data RX Digital Filter RX Data Loopback Multiplexer RX Data J1850_RX Freescale Semiconductor ...

Page 139

... BDLC State Vector Register (BDLC_DLCBSVR) 0x02–0x03 Reserved 0x04 BDLC Control Register 2 (BDLC_DLCBCR2) 0x05 BDLC Data Register (BDLC_DLCBDR) MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Table 6-1. Signal Properties Function Table 6-2. Table 6-2. BDLC memory map Register Byte Data Link Controller (BDLC) ...

Page 140

... CLKS DLOOP 4XE NBFS RXPOL BO4 BDLCE 2 3 Access Reset Value Section/Page R/W 0x50 6.3.2.5/6-14 R/W 0x00 6.3.2.6/6-16 R/W 0x00 6.3.2.7/6-17 R/W 0x00 6.3.2.8/6-18 Chapter 2, “System Configuration and Memory TEOD TSIFR TMIFR1 BO3 BO2 BO1 Freescale Semiconductor TMIFR0 D0 BO0 R0 BREAK ...

Page 141

... DLCBSTAT 6.3.2.1 BDLC Control Register 1 (BDLC_DLCBCR1) The BDLC Control Register 1 (BDLC_DLCBCR1) is used to configure and control the BDLC module. Address: Base + 0x00 IMSG CLKS W Reset 1 1 Figure 6-2. BDLC Control Register 1 (BDLC_DLCBCR1) MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Byte Data Link Controller (BDLC) ...

Page 142

... MPC5125 Microcontroller Reference Manual, Rev. 2 6-6 Description for a description of the conditions that cause Section 6.3.2.2, “BDLC State Vector Register bdlc. . Section 6.4.2.10, “J1850 VPW Valid/Invalid Bits and bdlc (BDLC_DLCBSVR).” Setting ) must always be 1.048576 MHz bdlc and how to clear interrupt Freescale Semiconductor ...

Page 143

... EOF flag is set. • No interrupts pending This interrupt cannot generate an interrupt of the CPU. Address: Base + 0x01 Reset 0 0 Figure 6-3. BDLC State Vector Register (BDLC_DLCBSVR) MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Byte Data Link Controller (BDLC) Access: User read-only ...

Page 144

... Setting SMRST arms the state machine reset generation logic. Setting SMRST does not affect BDLC module behavior in any way. MPC5125 Microcontroller Reference Manual, Rev. 2 6-8 Description . 4XE NBFS TEOD Description Access: User read/write TSIFR TMIFR1 TMIFR0 Freescale Semiconductor ...

Page 145

... When TEOD is used to end an IFR transmission, TEOD is cleared when the BDLC receives back a valid EOD symbol error condition or loss of arbitration occurs. 1 Transmit EOD symbol MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Byte Data Link Controller (BDLC) Description Section 6.4.4.1, “Protocol Architecture,” ...

Page 146

... If another node does transmit a successful IFR or a reception error occurs, the TSIFR bit is cleared. If not, the IFR is transmitted after the EOD of the next received message. MPC5125 Microcontroller Reference Manual, Rev. 2 6-10 Description Figure 6-5. The purpose of the in-frame response modes is to allow single Freescale Semiconductor ...

Page 147

... TMIFR1 bit is cleared and no attempt is made to retransmit the byte in the BDLC Data Register. If loss of arbitration occurs in the last bit of the IFR byte, two additional one bits (a passive long followed by an active short) is sent out. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Byte Data Link Controller (BDLC) NOTE 6-11 ...

Page 148

... IFR byte, two additional one bits (a passive long followed by an active short) is sent out. The extra logic is an enhancement to the J1850 protocol that forces a byte boundary condition fault. This helps prevent noise on the J1850 bus from corrupting a message. MPC5125 Microcontroller Reference Manual, Rev. 2 6-12 NOTE NOTE Freescale Semiconductor ...

Page 149

... Once the transmit shift register has shifted the first bit out, the TDRE flag is set, and the shadow register is ready to accept the next byte of data. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor CRC Type 0—No IFR ...

Page 150

... Also the polarity of the receive pin (J1850_RX) is set in this register. Read: any time MPC5125 Microcontroller Reference Manual, Rev Table 6-8. DLCBDR field descriptions Description Access: User read/write Freescale Semiconductor ...

Page 151

... MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor BO4 BO3 Description Table 6-10 for the BO[4:0] values corresponding to the expected transceiver delays and Corresponding Expected Transceiver’s delays (µs) ...

Page 152

... Write: write only once. Address: Base + 0x09 Reset 0 0 Figure 6-8. BDLC Rate Select Register (BDLC_DLCBRSR) MPC5125 Microcontroller Reference Manual, Rev. 2 6-16 Corresponding Expected Transmitter Symbol Timing Transceiver’s delays (µ Adjustment (t ) bdlc are supported as input bdlc Access: User read/write Freescale Semiconductor ...

Page 153

... The BDLC Control Register (BDLC_DLCSCR) enables the BDLC module. Address: Base + 0x0C Reset 0 0 Figure 6-9. BDLC Control Register (BDLC_DLCSCR) MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description ), which defines the basic timing resolution of the MUX Interface.The bdlc R[7:0] division 0x00 1 R[7:0] division 0x41 66 0x35 ...

Page 154

... MPC5125 Microcontroller Reference Manual, Rev. 2 6-18 Description ) enable/disable for power savings. bdlc ) is disabled, shutting down the BDLC module for power saving. Bus clocks bdlc ) and BDLC module are enabled to allow J1850 communications to take bdlc Access: User read/write TST_DIVTE TST_CRCV_ IDLE _T4 Freescale Semiconductor ...

Page 155

... All messages transmitted onto the J1850 bus must begin with an long active SOF symbol. This indicates to any listeners on the J1850 bus the start of a new message transmission. The SOF symbol is not used in the CRC calculation. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Description the BDLC module communicates across an SAE J1850 Message ...

Page 156

... Because an EOF symbol is longer than an EOD symbol response is transmitted after an EOD symbol, it becomes an EOF, and the message is assumed to be completed. The EOF flag is set upon receiving the EOF symbol. MPC5125 Microcontroller Reference Manual, Rev The remainder polynomial is initially (0xC4), regardless of the data contained in the message. If Freescale Semiconductor ...

Page 157

... Each message begins with an SOF symbol, an active symbol. Therefore, each data byte (including the CRC byte) begins with a passive bit, regardless of whether logic logic 0. All VPW bit lengths stated in the following descriptions are typical values at a 10.4 kbit/s bit rate. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Section 6.1.1, “Features.” Figure 6-12. ...

Page 158

... MPC5125 Microcontroller Reference Manual, Rev. 2 6-22 128 µ (a) Logic 0 128 µ (b) Logic 1 280 µ s EOF EOD (g) Inter-Frame Separator (IFS) Figure 6-12. J1850 VPW Symbols 64 µ µ s 200 µ s (d) End of Data 240 µ s (f) Break 20 µ s 300 µ s Figure 6-12(a)). Figure 6-12 (b)). Freescale Semiconductor ...

Page 159

... Because the minimum resolution of the BDLC module for determining which symbol is received equals a single period of the MUX Interface clock (t uncertainty due to sampling considerations. bdlc MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 6-12 (g)) ), the receiver symbol timing boundaries are subject to an bdlc Byte Data Link Controller (BDLC) ...

Page 160

... T tv5 ). The MUX bdlc Section 6.3.2.6, “BDLC Min Typ Max 126 128 130 126 128 130 198 200 202 162 164 166 238 240 242 298 300 302 Freescale Semiconductor Unit t bdlc t bdlc t bdlc t bdlc t bdlc t bdlc t bdlc t bdlc ...

Page 161

... Active Logic 1 5 Start of Frame (SOF) 6 End of Data (EOD) 7 End of Frame (EOF) 8 Inter-Frame Separator (IFS) 9 Break Signal (BREAK) Note: The receiver symbol timing boundaries are subject to an uncertainty MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Symbol Min T 65 tvp1 T 132 tvp2 T 132 tva1 T ...

Page 162

... Typ Max Unit bdlc bdlc bdlc bdlc bdlc bdlc bdlc — — t bdlc — — t bdlc Typ Max Unit bdlc bdlc bdlc bdlc bdlc bdlc bdlc — — t bdlc — — t bdlc (Invalid Passive Bit–Valid Table 6-16 Freescale Semiconductor ...

Page 163

... See rvp2(Max) Valid EOD Symbol If the passive to active transition beginning the next data bit or symbol occurs between the current symbol would be considered a valid EOD symbol. See rvp3(Max) MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 200 µs 128 µs T rvp1(Max rvp2(Min) ...

Page 164

... MPC5125 Microcontroller Reference Manual, Rev. 2 6-28 300 µ rv4(Max) rv4(Min) T rv5(Min) , the current symbol is considered a valid EOF symbol. (1) Valid EOF Symbol (2) Valid EOF+ IFS Symbol , the rv5(Min) Figure 6-14(2). All Freescale Semiconductor ...

Page 165

... See rva1(Max) Valid SOF Symbol If the active to passive transition beginning the next data bit or symbol occurs between the current symbol would be considered a valid SOF symbol. See rva3(Max) MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 200 µs 128 µs T rva2(Max rva1(Min) ...

Page 166

... However, if the BDLC module has lost arbitration due to noise on the bus, the two extra 1s ensure the current message is detected and ignored as a noise-corrupted message. MPC5125 Microcontroller Reference Manual, Rev. 2 6-30 T rv6(Min) Figure 6-16. J1850 VPW BREAK Symbol Figure 6-16. (2) Valid BREAK Symbol , the current symbol is considered rv6(Min) Freescale Semiconductor ...

Page 167

... The CRC error flag in the BDLC_DLCBSVR register is set when a CRC error is detected. If the interrupt enable bit (IE in the BDLC_DLCBCR1 register) is set, an interrupt request from the BDLC module is generated. Reading the BDLC_DLCBSVR register clears this flag. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ...

Page 168

... If the bus fault is temporary, as soon as the fault is cleared, the BDLC module resumes normal operation. If the bus fault is permanent, it may result in permanent loss of communication on the J1850 bus. MPC5125 Microcontroller Reference Manual, Rev. 2 6-32 and Invalid Active Bit, which define invalid symbols. The cycles before detecting an error. The analog bdlc Freescale Semiconductor ...

Page 169

... The MUX Interface is responsible for bit encoding/decoding and digital noise filtering between the Protocol Handler and the Physical Interface. Refer to MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor BDLC Module Function BDLC module immediately ceases transmitting. Further transmission and reception is disabled until a valid EOF symbol is detected. The symbol invalid or out of range flag is set and interrupt generated if enabled ...

Page 170

... If the signal on the J1850_RX signal transitions, there is a delay before that transition appears at the Filtered Rx Data output signal. This delay is between 15 and 16 clock periods, depending on where the MPC5125 Microcontroller Reference Manual, Rev. 2 6-34 4-Bit Up/Down Counter up/down out Figure 6-18. 4 Edge q d and Count Comparator Freescale Semiconductor Filtered Rx Data Out ...

Page 171

... Rx Shadow Register. The Tx Shift Register takes data, in parallel form, from the Tx Shadow Register and presents it serially to the State Machine so that it can be transmitted onto the J1850 bus. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor ) is 1.0486MHz, then the period (t bdlc Figure 6-1 ...

Page 172

... Shadow Register is loaded into the Tx Shift Register. After this transfer takes place, the Tx Shadow Register is ready to accept new data from the CPU. MPC5125 Microcontroller Reference Manual, Rev. 2 6-36 To Pad Drivers J1850_TX J1850_RX Loopback Multiplexer State Machine Tx Shift Register Tx Shadow Register Bus Interface and Rx/Tx Buffers Figure 6-19. BDLC Protocol Handler Outline BDLC 8 Freescale Semiconductor ...

Page 173

... BDLC module. Message reception is described in “Receiving A Message.” Later sections deal with transmitting and receiving In-Frame Responses on the SAE J1850 bus. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Byte Data Link Controller (BDLC) Figure 6-19) to either Section 6.4.6, ...

Page 174

... BDLC Data Register. After the BDLC module readies this byte for transmission, the BDLC_DLCBSVR register reflects that the next byte can be written to the BDLC Data Register (TDRE interrupt). MPC5125 Microcontroller Reference Manual, Rev. 2 6-38 Section 6.3.2.4, “BDLC Data NOTE Setting the TEOD bit Freescale Semiconductor ...

Page 175

... While this is the basic transmit flow, at times the message transmit process is interrupted. This can be due to a loss of arbitration to a higher priority message or due to an error being detected on the network. For the transmit routine, either of these events can be dealt with in a similar manner. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE NOTE NOTE ...

Page 176

... If an In-Frame Response (IFR) is received following the transmission of a message, the status indicating that an IFR byte has been received is indicated in the BDLC_DLCBSVR register before an EOF is indicated. Refer to Section 6.4.8, “Receiving An In-Frame Response (IFR),” manage the reception of IFR bytes. MPC5125 Microcontroller Reference Manual, Rev. 2 6-40 for a description of how to Freescale Semiconductor ...

Page 177

... DLCBSVR = 0x10? Load next byte to be BDLC_DLCBDR NOTE: The EOF and CRC error interrupts are handled in the BDLC Module Receive Routine Figure 6-20. Basic BDLC Transmit Flowchart MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor transmit routine No Is this the last BDLC_ No ...

Page 178

... IMSG bit should never be used to ignore the BDLC module’s own transmission. Because setting the IMSG bit prevents some BDLC_DLCBSVR register bits from being updated, it may be difficult for the CPU to complete the transmission correctly. MPC5125 Microcontroller Reference Manual, Rev. 2 6-42 Section 6.4.8, “Receiving An In-Frame Response (IFR).” NOTE Freescale Semiconductor ...

Page 179

... Setting the IMSG bit commands the BDLC module not to update the BDLC_DLCBSVR register until the next valid SOF is received. This prevents the CPU from having to service the BDLC module for each byte of every message sent over the network. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Byte Data Link Controller (BDLC) Figure 6-21. ...

Page 180

... As mentioned above, if one or more IFR bytes are received following the reception of a message, the status indicating the reception of the IFR byte(s) is indicated in the BDLC_DLCBSVR register before the EOF is indicated. Refer to Section 6.4.8, “Receiving An In-Frame Response (IFR),” deal with the reception of IFR bytes. MPC5125 Microcontroller Reference Manual, Rev. 2 6-44 for a description of how to Freescale Semiconductor ...

Page 181

... DLCBSVR = 0x1C/0x18? Yes Jump to Receive IFR handling routine Once BDLC module Yes detects EOF, DLCBSVR = 0x04? message reception is complete MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor receive routine BDLC_ Go to BDLC module Yes BREAK/Error handling (error detected) routine No BDLC_ Yes Read byte in ...

Page 182

... This IFR type not only acknowledges to the transmitter that the message was transmitted successfully, but also reveals which receivers actually received the message. As with the Type 1 IFR, no CRC byte is appended to the end of a Type 2 IFR. MPC5125 Microcontroller Reference Manual, Rev. 2 6-46 Freescale Semiconductor ...

Page 183

... BDLC module should be handled, refer to “Receiving An In-Frame Response (IFR).” Table 6-23. IFR Control Bit Priority Encoding READ/WRITE TSIFR TMIFR1 — MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor NOTE ACTUAL TMIFR0 TSIFR TMIFR1 0 0 — 1 — Byte Data Link Controller (BDLC) Section 6 ...

Page 184

... As with the TSIFR and TMIFR1 bits, the TMIFR0 bit must be set before the EOD symbol is received or it remains cleared and no IFR transmit attempts are made. The TMIFR0 bit is cleared after the CRC byte and EOD are transmitted error is detected on the bus loss of arbitration occurs during the IFR MPC5125 Microcontroller Reference Manual, Rev. 2 6-48 Freescale Semiconductor ...

Page 185

... IFR byte to the BDLC Data Register, replacing the previously written byte. This must be done before the first EOD symbol is received. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Byte Data Link Controller (BDLC) NOTE Figure 6-22 ...

Page 186

... MPC5125 Microcontroller Reference Manual, Rev. 2 6-50 BDLC_ No Yes DLCBSVR = 0x14? (LOA) No After BDLC module detects EOF, IFR transmit attempt is completed Exit Type 1 IFR transmit routine Figure 6-22. Transmitting A Type 1 IFR IFR byte is discarded Jump to receive IFR handling routine Freescale Semiconductor ...

Page 187

... SAE J1850 messages. The user should set the TEOD bit when the 11th byte is received, which prevents the 12-byte limit from being exceeded. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Byte Data Link Controller (BDLC) NOTE 6-51 ...

Page 188

... No IFR byte is discarded Jump to receive IFR handling routine EOF, IFR transmit attempt is complete Exit Type 1 IFR transmit routine Figure 6-23. Transmitting A Type 2 IFR No Was the eleventh MSG byte received? Yes Yes Set TEOD in DLCBCR2 Figure Freescale Semiconductor No 6-24. ...

Page 189

... Yes Jump to IFR receive routine Note: The EOF and CRC Error Interrupts are handled in the IFR Receive Routine MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Enter Type 3 IFR transmit routine Write first IFR byte to be transmitted into TMIFRDLCBDR Set desired TMIFR ...

Page 190

... TEOD bit (if set) is cleared, any IFR byte being transmitted is discarded and the loss of arbitration state is reflected in the BDLC_DLCBSVR register. Likewise error is detected MPC5125 Microcontroller Reference Manual, Rev. 2 6-54 the TMIFR1 bit should be set if the user NOTE NOTE Freescale Semiconductor ...

Page 191

... BDLC Data Register, and an RxIFR state is reflected in the BDLC_DLCBSVR register. No indication of the EOD reception in made because the RxIFR state indicates that the main portion of the message has ended and the IFR portion has begun. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Byte Data Link Controller (BDLC) NOTE 6-55 ...

Page 192

... BDLC_DLCBDR (RxIFR this an IFR transmit reflection? Store received IFR byte (in case of LOA) BDLC_ DLCBSVR = 0x04? (EOF) Store received No A Exit IFR receive routine B No Filter Received IFR Byte Yes Yes Is this IFR of any interest? IFR byte No B Set BDLC_DLCBCR1[IMSG] A Freescale Semiconductor ...

Page 193

... To transmit or receive these block mode messages, no extra BDLC module control functions must be performed. The user simply transmits or receives as many bytes as desired in one message frame, and the BDLC module operates message of normal length was being used. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Byte Data Link Controller (BDLC) Section 6.4.6.4, 6-57 ...

Page 194

... DLCBSVR=0x14? detects EOF, transmit (LOA) attempt is complete No BDLC_ No Attempt another transmission? DLCBSVR=0x10? (TDRE) Yes Exit BDLC module Load next byte to be transmit routine transmitted into BDLC_DLCBDR (clears TDRE byte? Yes Set Yes Jump to receive IFR handling routine No Yes C No Freescale Semiconductor ...

Page 195

... BDLC Baud Rate Select Register. The divisor should be chosen to generate a 1 MHz or 1.048576 MHz MUX interface clock (f Register, all of these bits become read only. 3. Initialize BDLC Control Register 2. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Figure 6-27. ). Following this write to BDLC Baud Rate Select bdlc ...

Page 196

... BDLC module interrupts of the CPU. 1. Clear Pending BDLC Interrupts To ensure that the BDLC module does not immediately generate a CPU interrupt when interrupts are enabled, the user should read the BDLC_DLCBSVR register to determine if any BDLC module MPC5125 Microcontroller Reference Manual, Rev. 2 6-60 Freescale Semiconductor ...

Page 197

... If the user chooses not to enable interrupts, BDLC_DLCBSVR must be polled periodically to ensure that state changes in the BDLC module are detected and dealt with appropriately. MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor Byte Data Link Controller (BDLC) 6-61 ...

Page 198

... Loopback Tests BDLC_DLCSCR[BDLCE] Exit loopback mode by clearing DLOOP Perform digital and analog loopback Enable BDLC module by setting BDLC_DLCSCR[BDLCE] Exit loopback mode Read BDLC_DLCBSVR Is No BDLC_DLCBSVR = 0x00? Yes Set BDLC_DLCBCR1[IE] to enable interrupts Proceed to remaining MCU initialization by setting mode Tests by clearing DLOOP Freescale Semiconductor ...

Page 199

... ROM device to SDRAM. The e300c4 core can execute code from the on-chip SRAM. The e300c4 core has memory mapped access to all resources, including: • All on-chip programming registers • External SDRAM • Internal SRAM MPC5125 Microcontroller Reference Manual, Rev. 2 Freescale Semiconductor 7-1 ...

Page 200

... Enabling of the address or data parity error check by setting the HID0[EBA, EBD] bits generates a machine check exception or a checkstop depending on the HID0[EMCP] bit. MPC5125 Microcontroller Reference Manual, Rev. 2 7-2 Table 7-1. ID Values for the MPC5125 M01S Mask Set PVR 0x8086_2010 MPC5125 SVR 0x8019_0010 JTAG ID Code 0x0540_C01D Freescale Semiconductor ...