MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 364

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Fast Ethernet Controller (FEC)
1
2
3
4
14.3.4
Table 14-4
where hardware-maintained counters reside. These fall in the 0x0200–0x03FF address offset range. The
counters are divided into two groups.
RMON counters cover the Ethernet statistics counters defined in RFC 1757. In addition to the counters
defined in the Ethernet statistics group, a counter is included to count truncated frames because the FEC
14-8
FEC1: 0xFF40_2800
FEC2: 0xFF40_4800
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
In this column, R/W = Read/Write, R = Read-only, and W = Write-only.
In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated description for
more information.
Reset value is indeterminate.
0x18C–0x1F0
0x0F0–0x117
0x154–0x17F
0x1F8–0x1FF
0x128–0x143
FEC_BASE
Offset from
0x0EC
0x11C
0x14C
0x1F4
0x118
0x120
0x124
0x144
0x148
0x150
0x180
0x184
0x188
defines the MIB counters memory map, which defines the locations in the MIB RAM space
MIB Block Counters Memory Map
1
ETH_OP_PAUSE—Opcode/Pause Duration Register
Reserved
ETH_IADDR1—Descriptor Individual Address 1
ETH_IADDR2—Descriptor Individual Address 2
ETH_GADDR1—Descriptor Group Address 1
ETH_GADDR2—Descriptor Group Address 2
Reserved
ETH_X_WMRK—FIFO Transmit FIFO Watermark
Reserved
ETH_R_BOUND—FIFO Receive Bound Register
ETH_R_FSTART—FIFO Receive Start Register
Reserved
ETH_R_DES_START—Beginning of Receive Descriptor
Ring
ETH_X_DES_START—Beginning of Transmit Descriptor
Ring
ETH_R_BUFF_SIZE—Receive Buffer Size Register
Reserved
ETH_DMA_CONTROL—DMA Function Control Register
Reserved
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 14-3. FEC memory map (continued)
Register
Chapter 2, “System Configuration and Memory
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
2
0x0001_UUUU
Reset Value
0x0000_0000
0x0000_0600
0x0000_0500
0xU000_0000
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Freescale Semiconductor
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