MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 539

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Note:
Note:
Freescale Semiconductor
J1850_RX
TCK
TDI
TDO
TMS
TRST
PORESET
HRESET
SRESET
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
If RST_CONF_LOC[1:0] = 01, the reset value[6:0] = 7’b00_000_00.
If RST_CONF_LOC[1:0] = 01, the reset value[6:0] = 7’b00_110_00.
If RST_CONF_LOC[1:0] = 01, the reset value[6:0] = 7’b00_110_00. If RST_CONF_LOC[1] = 1, the reset
value[6:0] = 7’b00_110_11.
If RST_CONF_LOC[1:0] = 10, the reset value[6:0] = 7’b01_000_11. If RST_CONF_LOC[1:0] = 00, the reset
value[6:0] = 7’b00_000_11.
If RST_CONF_LOC[1:0] = 00 and RST_CONF_MX = 0, the reset value[6:0] = 7’b11_000_11.
If RST_CONF_LOC[1:0] = 11, the reset value[6:0] = 7’b11_000_11.
Not controlled by I/O Control registers.
8
PAD Name
8
8
8
8
RST_CONF_LOC[1:0] is defined as:
2’b00: Boot from LPC.
2’b01: boot From NFC.
If RST_CONF_LOC[1] = 1, the slew rate of pad is fastest, and thus the reset value[1:0] = 11.
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8
8
IOCONTROL_BASE
(0xFF40_A000)
Offset from
0x81
Table 20-6. Pad I/O Control Register Table (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
1
STD_PU_ST
STD_PU_ST
STD_PU
STD_PU
STD_PU
STD_PU
STD_PU_ST
STD_PU_ST
STD_PU_ST
Type
0x18
7’b00_110_00
0x04
7’b00_001_00
0x18
7’b00_110_00
0x03
7’b00_000_11
0x18
7’b00_110_00
0x18
7’b00_110_00
0x1C
7’b00_111_00
0x1F
7’b00_111_11
0x1F
7’b00_111_11
Reset Value [6:0]
Chapter 2, “System Configuration and Memory
00 J1850_RX
01 Reserved
10 NFC_RB3
11 I2C1_SDA
FUNCMUX
I/O Control
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