MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 576

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LocalPlus Bus Controller (LPC)
21.3.2.3
After reset, the core can fetch the first instruction from the LPC. The chip select boot (CSBoot) is dedicated
for this purpose. CSBoot and CS0 are physically the same pins. The difference is that CSBoot is affected
by the reset configuration and is enabled after reset.
Several options are available for this purpose:
21.3.2.4
All chip selects (CS0–7) have the same functionality. Only one CS can be active at any given time. If an
address hit is located in multiple CS windows, only the CS with the highest priority becomes active. The
CS with the lowest number has the highest priority (CS0 = highest priority, CS7 = lowest priority).
CSBoot and CS0 are identical with the exception of their access window registers, contained in the
XLBMEN register map (LocalPlus Boot/CS0–7 Access Window Registers (LPBAW/LPCSxAW)).
CSBoot and CS0 are physically the same pins. The difference is that the CSBoot access window is affected
by the reset configuration and is the only enabled chip select after reset.
21-36
AD[31:0] (wr)
•
•
•
NOTES:
ALE can be active high or low. This diagram shows an active low scenario.
The length of the address latch and of the isolation cycle can be configured by the ALEN bit of the CSBOOT/CSX
configuration register. This diagram shows a setting of 0.
This diagram represents a wait state setting of 1.
Address Latch bit are set to zero. CS is asserted together with ALE.
Muxed or non-muxed mode
Byte or short word addressing
Data size can be 8, 16, or 32 bits
Burst
CLK
R/W
ALE
CSx
TS
Boot Configuration
Chip Selects Configuration
Figure 21-31. T
Address Tenure
Address
Latch
Address
MPC5125 Microcontroller Reference Manual, Rev. 2
Isolation
i
ming Diagram—Muxed Synchronous Write Burst
Data Tenure
Valid Write Data
Freescale Semiconductor