MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 885

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

notified again after the reset is complete via the enable change bit in the USB_PORTSCn register that
causes a port change interrupt.
This assist ensures the OTG parameter TB_ACON_BSE0_MAX = 1 ms is met.
32.4.2.2
Writing a one to HADP starts a data pulse of approximately 7ms in duration and then automatically cease
the data pulsing. During the data pulse, the DP is set and then cleared. This automation relieves software
from accurately controlling the data-pulse duration. During the data pulse, the HCD can poll to see that the
HADP and DP bit have returned low to recognize the completion or simply launch the data pulse and wait
to see if a VBUS Valid interrupt occurs when the A-side supplies bus power.
This assist ensures data pulsing meets the OTG requirement of > 5 ms and < 10 ms.
32.4.2.3
During HNP, the B-disconnect occurs from the OTG A_suspend state and within 3 ms, the A-device must
enable the pullup on the DP leg in the A-peripheral state. When HABA is set, the Host Controller port is
in suspend mode, and the device disconnects, then this hardware assist begins.
When software has enabled this hardware assist, it must not interfere during the transition and should not
write any register in the core until it gets an interrupt from the device controller signifying that a reset
interrupt has occurred or at least first verify that the core has entered device mode. HCD/DCD must not
activate the core soft reset at any time since this action is performed by hardware. During the transition,
the software may see an interrupt from the disconnect and/or other spurious interrupts (i.e., SOF/etc.) that
may or may not cascade and my be cleared by the soft reset depending on the software response time.
After the core has entered device mode by the hardware assist, the DCD must ensure that the
ENDPTLISTADDR is programmed properly before the host sends a setup packet. Since the end of the
reset duration, which may be initiated quickly (a few microseconds) after connect, requires at a minimum
50 ms, this is the time for which the DCD must be ready to accept setup packets after having received
notification that the reset has been detected or simply that the OTG is in device mode which ever occurs
first.
In the case where the A-peripheral fails to see a reset after the controller enters device mode and engages
the DP-pullup, the device controller interrupt the DCD signifying that a suspend has occurred.
This assist ensures the parameter TA_BDIS_ACON_MAX = 3 ms is met.
Freescale Semiconductor
1. Reset the OTG core.
2. Write the OTG core into device mode.
3. Write a 1 to the device run bit and enable necessary interrupts including:
a) USB Reset Enable (URE); enables interrupt on USB bus reset to device.
b) Sleep Enable (SLE); enables interrupt on device suspend.
c) Port Change Detect Enable (PCE); enables interrupt on device connect.
Data-Pulse
B-Disconnect to A-Connect
MPC5125 Microcontroller Reference Manual, Rev. 2
Universal Serial Bus Interface with On-The-Go
32-57