MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 134

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocks and Low-Power Modes
5.3.1.27
The System Clock Frequency Register (SCFR3) is shown in
controlled by this register provides a clock with a programmable high and low phase.
5-34
NFC_RATIO_H NFC fractional clock divider ratio. The clock high phase is defined by the NFC_RATIO_H parameter, the low
Address: Base + 0x80
Reset
Reset
Field
W
W
R
R
16
0
0
0
0
System Clock Frequency Register (SCFR3)
phase by NFC_RATIO_L. The divide values for the high phase of the clock are as follows:
The NFC flash_clock frequency = SYS_CLK/ (NFC_RATIO_H/4 + NFC_RATIO_L/4), with the reset value:
NFC flash_clock is 400/(40/4 + 96/4) = 11.76 MHz.
17
0
0
0
1
18
1
0
0
2
CSB_CLK:NFC_CLK
Figure 5-32. System Clock Frequency Register (SCFR3)
NFC_RATIO_H
19
10 (default)
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
62.75
63.25
63.75
3.25
3.75
4.25
63.5
3.5
n/4
n/4
63
3
4
Table 5-32. SCFR3 field descriptions
20
4
1
0
0
21
0
0
0
5
22
0
0
0
6
0b1111_1011 (251d)
0b1111_1100 (252d)
0b1111_1101 (253d)
0b1111_1110 (254d)
0b1111_1111 (255d)
0b0000_1100 (12d)
0b0000_1101 (13d)
0b0000_1110 (14d)
0b0000_1111 (15d)
0b0001_0000 (16d)
0b0001_0001 (17d)
0b0010_1000 (40d)
Field value
23
0
0
0
7
Description
n
n
24
Figure
8
0
0
0
25
9
1
0
0
5-32. The NFC fractional clock divider
10
26
1
0
0
NFC_RATIO_L
11
27
0
0
0
12
28
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
14
30
0
0
0
15
31
0
0
0