MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 542

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

LocalPlus Bus Controller (LPC)
21-2
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•
•
•
•
•
•
•
Interface to memory mapped or chip selected devices
Two main modes of operation:
— Non-muxed modes
— Muxed modes (address latch enable (ALE) used)
8 chip-select (CS) signals
— Programmable wait states per CS
— Programmable deadcycles per CS
— Programmable holdcycles per CS
— Programmable byte swapping per CS
Configurable boot interface supporting Power Architecture architecture code execution
Dynamic bus sizing
Support of burst mode flash devices (up to 32 byte bursts)
— Synchronous burst read
— Synchronous burst write
— Asynchronous burst read (page mode)
— Asynchronous burst write (page mode)
DMA support allows data movement independently from the CPU (up to 56 byte bursts)
No support of misaligned accesses. This also includes transfers of 3, 5, 6, and 7 bytes.
LPC_CLK
TSIZ[1:0]
AD[31:0]
AX[31:0]
– Address up to 32 bits, data 8, 16, or 32 bits
– Address up to 32 bits, data 8, 16, or 32 bits
– Programmable ALE level
CS[7:0]
Name
ACK
R/W
OE
TS
Address and data lines
Non-muxed mode: address lines
Muxed mode: address latch enable (AX[0])
Transfer size (AX[2:1])
Transfer start (AX[3])
No burst transaction: Acknowledge can shorten a transaction
Burst transaction: Indicates that a burst transaction is ongoing.
LPC clock
Chip select
Output enable
Read/write bar
Transfer size
Transfer start
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 21-1. Signal Properties
Function
I/O Reset
I/O
I/O
O
O
O
O
O
O
O
—
—
Freescale Semiconductor
0
0
1
1
1
0
0
Pullup
Pullup
—
—
—
—
—
—
—
—