MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 981

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

It is also not necessary to initially prime Endpoint 0 because the first packet received is always a setup
packet. The contents of the first setup packet requires a response in accordance with USB device
framework command set.
32.8.2
From a chip or system reset, the USB controller enters the powered state. A transition from the powered
state to the attach state occurs when the run/stop bit is set to 1. After receiving a reset on the bus, the port
enters the defaultFS or defaultHS state in accordance with the protocol reset described in Appendix C.2 of
the USB Specification Rev. 2.0. The following state diagram
device.
States powered, attach, defaultFS/HS, and suspendFS/HS are implemented in the USB controller and are
communicated to the DCD using these bits:
Freescale Semiconductor
3. Program the PTS field of the USB_PORTSCn register if using a non-ULPI PHY.
4. Set iodis_b bit in the CONTROL register to enable PHY interface.
5. Allocate and Initialize device queue heads in system memory Minimum: Initialize device queue
6. Configure USB_ENDPOINTLISTADDR Pointer.
7. Enable the microprocessor interrupt associated with the USB controller and optionally change
8. Set run/stop bit to run mode.
heads 0 Tx and 0 Rx.
For information on device queue heads, refer to
For additional information on USB_ENDPOINTLISTADDR, refer to the register table.
setting of ITC field in USB_USBCMD register.
Recommended: Enable all device interrupts including: USBINT, USBERRINT, port change
detect, USB reset received, and DCSuspend.
For a list of available interrupts, refer to the USB_USBINTR and the USB_USBSTS register
tables.
After the run bit is set, a device reset occurs. The DCD must monitor the reset event and set the
USB_DEVICEADDR register, set the USB_ENDPTCTRLn registers, and adjust the software state
as described in the bus reset section of the following port state and control section below.
Port State and Control
All device queue heads must be initialized for control endpoints before the
endpoint is enabled. Device queue heads for non-control endpoints must be
initialized before the endpoint can be used.
Endpoint 0 is a control endpoint only and does not need to be configured
using USB_ENDPTCTRL0 register.
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
NOTE
Section 32.7, “Device Data Structures.”
(Figure
32-74) depicts the state of a USB 2.0
Universal Serial Bus Interface with On-The-Go
32-153