MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 46

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Configuration and Memory Map (XLBMEN + Mem Map)
2.2.5.1.8
Figure 2-7
depends on the reset configuration word. See
for a detailed description.
2.2.5.1.9
The Power Architecture core may use a local bus peripheral device to fetch its boot vector. For this
purpose, NFCBAR[BASE_ADDR] reset value is set according to the value set in the reset configuration
word high BMS and ROM_LOC fields.
Table 2-12
2-12
Address: Base + 0x00C8
BASE_ADDR
BASE_ADDR
Reset
Reset
Field
Field
W
W
R
R
16
shows the NFC Base Address Register (NFCBAR). The NFCBAR[BASE_ADDR] reset value
0
0
0
defines the reset value NFCBAR[BASE_ADDR].
Although 256 KB memory space is reserved, the real SRAM size is 32 KB.
Any address in a 256 KB window is directed into 32 KB memory by
modulo 32 KB.
NFC Base Address Register (NFCBAR)
NFCBAR[BASE_ADDR] Reset Value
Identifies the 14 most-significant address bits of the base address of the 256 KB SRAM memory window.
Identifies the 12 most-significant address bits of the base address of the 1 MB NFC memory window.
17
0
0
1
18
0
0
2
Figure 2-7. NFC Base Address Registers (NFCBAR)
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 2-10. SRAMBAR field descriptions
Table 2-11. NFCBAR field descriptions
20
4
0
0
See
BASE_ADDR
21
0
0
5
Table 2-12
Section 2.2.5.1.9, “NFCBAR[BASE_ADDR] Reset Value,”
22
0
0
6
NOTE
23
0
0
7
Description
Description
24
8
0
0
25
9
0
0
10
26
0
0
11
27
0
0
12
28
0
0
0
0
Freescale Semiconductor
Access: User read/write
13
29
0
0
0
0
14
30
0
0
0
0
15
31
0
0
0
0