MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 48

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

System Configuration and Memory Map (XLBMEN + Mem Map)
2.2.6
It is generally a programming error to overlap the addressing range of the Local Access Windows. Nothing
prevents software from programming overlapping addresses.
2.2.7
After a local access window is enabled, it should not be modified while any device in the system may be
using the window. Neither should a new window be used until the effect of the write to the window is
visible to all blocks that use the window. This can be guaranteed by completing a read of the last local
access window configuration register before enabling any other devices to use the window. For instance,
if LPC local access windows 1–3 are being configured in order during the initialization process, the last
write (to LPCS2AW) should be followed by a read of LPCS2AW before any devices try to use any of these
windows. If the configuration is being done by the local Power Architecture processor, the read of
LPCS2AW should be followed by an isync instruction.
2.3
Some general information and configuration options that affect the system behavior and performance are
described in the following sections.
2-14
0xFFFF_FFFF
0x000F_FFFF
0x007F_FFFF
0x400F_FFFF
0x0100_FFFF
0xFFF0_0000
0xFF80_0000
0x0000_0000
0x0100_0000
0x4000_0000
Figure 2-8. Initial Memory Map Configurations Immediately After the Release of PORESET
System Configuration
Overlap of Local Access Windows
Configuring Local Access Windows
LPC BOOT ROM
ROM_LOC = 00
BMS = 0
NAND FLASH
MPC5125 Microcontroller Reference Manual, Rev. 2
LPC BOOT ROM
ROM_LOC = 00
BMS = 1
NAND FLASH
LPC BOOT ROM
ROM_LOC = x1
BMS = 0
NAND FLASH
LPC BOOT ROM
ROM_LOC = x1
BMS = 1
NAND FLASH
Freescale Semiconductor
LPC BOOT ROM
ROM_LOC = x0
BMS = x
NAND FLASH