MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 729

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

25.5.3.3
A General-Purpose I/O (GPIO) must be used as an AC97 reset output pin. The PSC monitors the first
three time slots of each Tx frame to detect the power-down condition for the AC97 digital interface. The
power-down condition is detected as follows:
Low-power mode can be left through a warm or cold reset. The CPU does a warm reset by setting
SICR[AWR] for at least 1µs. This asserts the FRAME frame sync output in AC97 mode. The CPU does
a cold reset in two steps:
25.5.3.4
The data transmission is the standard AC97 one, see
Definition for AC97
transmit site and analyzes received time slot0,1, and 2. The used data slots (3 to 12) must be in the FIFOs.
The RX_SLOTS field in the AC97Slots register specify the expected RX data slots. If the received slots
do not match this specification, the receiver ignores all data slots from the current frame and sets the
SR[UNEX_RX_SLOT] bit. Only the expected and valid tagged data slots are in the RxFIFO. This
functionality guarantees the software can assign the data in the RxFIFO to an AC97 slot. Only the order
in the RxFIFO marks the AC97 slot number.
The TX_SLOTS field in the AC97Slots register defines which data slots are sent. All data for these slots
must be in TxFIFO. The transmitter generates the related slot0 tag data. If the TxFIFO is empty, the
transmitter tags the frame as empty. The transmitter sends data if the receiver detects the codec ready state
for the current frame. the Tx FIFO contains the specified data words (defined in the AC97Slots register),
and the slot request for the specified slots was active (slot request bit was zero in the previous frame). If
the AC97 codec set a slot request to one, the transmitter sends a complete empty frame because the
transmitter is cannot send a port of the required slots without changing the order of the data in the FIFO.
If the software sends a command to the AC97 codec, the control register index and the control register
write data values must be written to the AC97CMD register. A write access to any word of this register
triggers the transmitter to send out the register value, synchronous the SR[CMD_SEND] bit was set. The
transmitter generates a slot0 tag that marks slot1 and slot2 as valid slot. If the receiver was able to send out
the command data, the SR[CMD_SEND] bit is cleared.
Freescale Semiconductor
1. The first three bits of slot 1 must be set, indicating Tx frame and slots 1 and 2 are valid.
2. Slot 2 holds the power-down register (0x26) address in the external AC97 device.
3. Slot 3 has one in the fourth bit (bit 12/PR4 in power-down register 1), as defined in the AC97
1. Writes 0 to whichever GPIO is the active low AC97 reset pin for the minimum time specified in
2. Writes 0 to PSC1 or PSC2 SICR[ACRB]. CPU should set this bit after writing 1 to the GPIO used
specification.
the AC97 specification.
for the AC97 reset pin.
AC97 Low-Power Mode
Transmitting and Receiving in AC97 Mode
Step 2 (above) is required so the PSC knows when an AC97 cold reset is
occurring.
Mode”. The AC97 controller is able to generate the time slot0,1 and 2 data on the
MPC5125 Microcontroller Reference Manual, Rev. 2
NOTE
Section 25.5.3.1, “Block Diagram and Signal
Programmable Serial Controller (PSC)
25-51