MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 219

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.4.2
The following error handling sequence is recommended:
Freescale Semiconductor
2. Write to ATER to define which events are considered error events and which are not.
3. Write to AERR to define whether different error events cause a reset request or an interrupt.
4. Write to AIDR to define the kind of interrupt (regular or MCP) that is caused by every error event.
5. Write to AMR to enable interrupts.
6. Write to ATR to set the ATO and DTO timers. This is necessary only if the required timers are set
1. Read AER to find out about the error that occurred in the system. Also, read the values of AEATR
2. If those registers are not accessible because of a stalled bus, reset the chip and read the values of
3. Clear all the previous events by writing 1s to AER. This register is also cleared after reset.
This is necessary only if interrupts are enabled and AERR defines error events to generate
interrupts.
to less than their maximum value (the default).
and AEADR to check on the first error event in the system.
the AEATR and AEADR registers to check on the event that caused this problem to the system.
Use HRESET to reset the chip to guarantee that the information stored in AEATR and AEADR is
not lost.
Error Handling Sequence
MPC5125 Microcontroller Reference Manual, Rev. 2
CSB Arbiter and Bus Monitor
8-19