MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 891

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

pointers allow for 3 (transactions) × 1024 (maximum packet size × 8 (transaction records) = 24,576 bytes
to be moved with this data structure, regardless of the alignment offset of the first page.
Because each pointer is a 4K aligned page pointer, the least significant 12 bits in several of the page
pointers are for other purposes.
Freescale Semiconductor
Buffer Pointer
Buffer Pointer
Buffer Pointer
Packet Size
Maximum
(Page 0)
Address
(Page 1)
(Page 2)
Device
EndPt
31:12
31:12
Field
31:12
Field
Field
10:0
11:2
Mult
11:8
I/O
1:0
6:0
11
7
This is a 4 K aligned pointer to physical memory. Corresponds to memory address bits [31:12].
This 4-bit field selects the particular endpoint number on the device serving as the data source or sink.
Reserved. Reserved for future use and should be initialized by software to 0.
This field selects the specific device serving as the data source or sink.
This is a 4 K aligned pointer to physical memory. Corresponds to memory address bits [31:12].
Direction (I/O). This field encodes whether the high-speed transaction should use an IN or OUT PID.
0 OUT
1 IN
This directly corresponds to the maximum packet size of the associated endpoint (wMaxPacketSize). This field
is used for high-bandwidth endpoints where more than one transaction is issued per transaction description
(.for example, per micro-frame). This field is used with the Multi field to support high-bandwidth pipes. This field
is also used for all IN transfers to detect packet babble. Software should not set a value larger than 1024 (400h).
Any larger value yields undefined results.
This is a 4 K aligned pointer to physical memory. Corresponds to memory address bits [31:12].
Reserved. This bit reserved for future use and should be cleared.
This field is used to indicate to the host controller the number of transactions that should be executed per
transaction description (for example, per micro-frame). The valid values are:
00 Reserved. A 0 in this field yields undefined results.
01 One transaction to be issued for this endpoint per micro-frame
10 Two transactions to be issued for this endpoint per micro-frame
11 Three transactions to be issued for this endpoint per micro-frame
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 32-47. iTD Buffer Pointer Page 1 (Plus)
Table 32-48. Buffer Pointer Page 2 (Plus)
Table 32-46. Buffer Pointer Page 0 (Plus)
Description
Description
Description
Universal Serial Bus Interface with On-The-Go
32-63