MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 907

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.6.1
After initial power-on or HCReset (hardware or via HCReset bit in the USB_USBCMD register), all of
the operational registers are at their default values, as illustrated in
only the operational registers not contained in the auxiliary power well is at their default values.
To initialize the host controller, software should perform the following steps:
At this point, the host controller is running and the port registers begin reporting device connects. System
software can enumerate a port through the reset process (where the port is in the enabled state). At this
point, the port is active with SOFs occurring down the enabled port enabled high-speed ports, but the
schedules have not yet been enabled. The EHCI host controller does not transmit SOFs to enabled full- or
low-speed ports.
To communicate with devices via the asynchronous schedule, system software must write the
ASYNDLISTADDR register with the address of a control or bulk queue head. Software must then enable
the asynchronous schedule by writing a one to the asynchronous schedule enable bit in the
Freescale Semiconductor
1. Optionally set streaming disable in the USB_USBMODE register.
2. Optionally modify the USB_BURSTSIZE register.
3. Program the PTS field of the USB_PORTSCn register if using a non-ULPI PHY.
4. Set the USB_EN bit in the CONTROL register.
5. Program the CTRLDSSEGMENT register with 4-Gigabyte segment where all of the interface data
6. Write the appropriate value to the USB_USBINTR register to enable the appropriate interrupts.
7. Write the base address of the periodic frame list to the PERIODICLIST BASE register. If there are
8. Write the USB_USBCMD register to set the desired interrupt threshold, frame list size (if
structures are allocated.
no work items in the periodic schedule, all elements of the periodic frame list should have their
T-Bits set.
applicable), and turn the controller by setting the run/stop bit.
Host Controller Initialization
USB_PERIODICLISTBASE
USB_ASYNCLISTADDR
Operational Register
USB_CONFIGFLAG
CTRLDSSEGMENT
USB_PORTSCn
USB_USBCMD
USB_USBINTR
USB_FRINDEX
USB_USBSTS
Table 32-68. Default Values of Operational Register Space
MPC5125 Microcontroller Reference Manual, Rev. 2
(0x0008_0B00 if Asynchronous Schedule Park Capability is set)
0x0000_1000
0x0000_0000
0x0000_0000
0x0000_0000
Undefined
Undefined
0x0000_0000
0x0000_2000 (w/PPC set);
0x0000_3000 (w/PPC cleared)
0x0008_0000
Default Value (after Reset)
Table
Universal Serial Bus Interface with On-The-Go
32-68. After a hardware reset,
32-79