MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 311

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
•
•
•
•
•
•
•
Master buses
— Four incoming master buses
— Supports 16-byte and 32-byte bursts
— Supports byte enables
— Supports 4-bit priority signal for each bus.
Arbitration protocol
— Inside the arbiter block, there are a total of six different arbiters that each take out the highest
— After the first prioritization, the next round of arbitrating between the different arbiters is done.
Write buffer contains five 32-byte entries.
Supports 16- and 32-bit-wide DDR1/DDR2 and Mobile-DDR DRAM devices
Supports 32-bit-wide SDR devices
Controller supports two chip selects, 8 banks per chip select (16 banks total).
Supports dynamic on-die termination in the host device and in the DRAM.
priority request in a certain class. All the arbiters are DRAM state aware, meaning they
disregard requests that cannot be sent to the DRAM because of DRAM timing limitations.
– Arbiter 1: Looks for highest priority read command
– Arbiter 2: Looks for highest priority write command
– Arbiter 3: Looks for highest priority activate-for-read command
– Arbiter 4: Looks for highest priority activate-for-write command
– Arbiter 5: Looks for highest priority precharge-for-read command
– Arbiter 6: Looks for highest priority precharge-for-write command
A fixed-priority schema is followed:
– Read and write commands have highest priority
– Activate has next-highest priority
– Precharge has lowest priority
– The DRAM is in read or write mode. In read mode, reads have priority over writes. In write
– DRAM only switches from read to write mode or vice-versa if:
mode, writes have priority over read.
A high-priority write is found, and the write buffer is full.
A high-priority read is found.
The device is in read mode, but no more reads pending
The device is in write mode, but no more writes pending.
MPC5125 Microcontroller Reference Manual, Rev. 2
DRAM Controller
11-3