MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 201

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 8
CSB Arbiter and Bus Monitor
8.1
This chapter describes the Coherent Systems Bus (CSB) arbiter in the MPC5125 device. In addition, it
describes the configuration, control, and status registers of the arbiter.
The CSB arbiter is responsible for providing coherent system bus arbitration. It tracks all the address and
data tenures, and provides all the arbitration signals to masters and slaves. In addition, it monitors the bus
and reports on errors and protocol violations.
8.1.1
The CSB arbiter includes the following features:
8.1.1.1
Coherent system bus is the central bus. Any data transaction from master to slave in the device passes
through the coherent system bus. The coherent system bus supports pipelined transactions. It has
independent address and data tenures. Pipeline depth determines the number of address tenures that can be
started before the first data tenure is finished.
Basic burst size is equal to cache line length, which is 32 bytes. Using repeat request mode enables as many
as eight consecutive bursts to be executed by the same master. The maximum number of consecutive
Freescale Semiconductor
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Supports a programmable pipeline depth (from 1 to 4)
Supports four levels of priority for bus arbitration
Supports repeat request mode: number of programmable consecutive transactions from the same
master (as many as eight transactions)
Supports data streaming operations
Supports programmable address bus parking mode: disable, park to last bus owner, park to s/w
selected master
Claims address only, reserved, and illegal transaction types, report on it and can raise maskable
interrupt
Provides timers for address tenure time-out and data tenure time-out detection and can issue
maskable interrupt, if any timer expired
Reports on transfer error and can issue maskable interrupt
Can issue regular or machine check interrupt for each type of error event (programmable)
Introduction
Features
Coherent System Bus Overview
MPC5125 Microcontroller Reference Manual, Rev. 2
8-1