MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 978

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.7.1.4
The set-up buffer is dedicated storage for the 8-byte data that follows a set-up PID.
32.7.2
The dTD describes to the device controller the location and quantity of data sent/received for given
transfer. The DCD should not attempt to modify any field in an active dTD except the next link pointer,
which should only be modified as described in
Descriptors.”
32-150
32-bit
word
1
2
31
0
30
31:0
31:0
Bits
Endpoint Transfer Descriptor (dTD)
29
Set-up Buffer
Each endpoint has a TX and an RX dQH associated with it, and only the RX
queue head is for receiving setup data packets.
28
Device Controller Read/Write
27
Setup Buffer 0. This buffer contains bytes 3 to 0 of an incoming setup buffer packet and the device
controller writes it for software to read.
Setup Buffer 1. This buffer contains bytes 7 to 4 of an incoming setup buffer packet and the device
controller writes it for software to read.
26
25
Buffer Pointer (Page 0)
Buffer Pointer (Page 1)
Buffer Pointer (Page 2)
Buffer Pointer (Page 3)
Buffer Pointer (Page 4)
24
Total Bytes
This bitmap needs to be redrawn
Figure 32-73. Endpoint Transfer Descriptor (dTD)
23
MPC5125 Microcontroller Reference Manual, Rev. 2
22
21
Table 32-85. Multiple Mode Control
Next Link Pointer
20
19
18
17
Section 32.8.7, “Managing Transfers with Transfer
16
NOTE
ioc
15
Device Controller Read Only.
14
13
0
Description
12
MultO
11
0
10
9
0
8
Current Offset
Frame Number
7
Reserved
Reserved
Reserved
6
5
Status
4
3
0
Freescale Semiconductor
2
1
T
0