MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 937

IC MCU 32BIT E300 324TEPBGA

MPC5125YVN400

Manufacturer Part Number
MPC5125YVN400
Description
IC MCU 32BIT E300 324TEPBGA
Manufacturer
Freescale Semiconductor
Series
MPC51xxr

Specifications of MPC5125YVN400

Core Processor
e300
Core Size
32-Bit
Speed
400MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, USB OTG
Peripherals
DMA, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.33 V ~ 1.47 V
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
324-PBGA
Processor Series
MPC51xx
Core
e300
Data Bus Width
32 bit
Development Tools By Supplier
TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
Maximum Clock Frequency
400 MHz
Operating Supply Voltage
1.4 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
3.3 V
Interface Type
CAN, I2C
Minimum Operating Temperature
- 40 C
Program Memory Size
32 bit
Cpu Speed
400MHz
Embedded Interface Type
CAN, I2C, SPI, UART, USB
Digital Ic Case Style
TEPBGA
No. Of Pins
324
Rohs Compliant
Yes
Cpu Family
MPC5xx
Device Core Size
32b
Frequency (max)
400MHz
Total Internal Ram Size
32KB
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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result area is written back to the transfer result area of the target qTD. This state is also referred to as: qTD
retirement. The fields that must be written back to the source qTD include Total Bytes to Transfer, Cerr,
and Status.
The duration of this state depends on when the qTD write-back has been committed.
32.6.9.5
The host controller must use the horizontal pointer in the queue head to the next schedule data structure
when any of the following conditions exist:
There is no functional requirement that the host controller wait until the current transaction is complete
before using the horizontal pointer to read the next linked data structure. However, it must wait until the
current transaction is complete before executing the next data structure.
32.6.9.6
A qTD has an array of buffer pointers used to reference the data buffer for a transfer. The EHCI
specification requires the buffer associated with the transfer be virtually contiguous. If the buffer spans
more than one physical page, it must obey the following rules:
Figure 32-62
Freescale Semiconductor
If the Active bit is a one on exit from the Execute Transaction state, or
When the host controller exits the Write Back qTD state, or
If the Advance Queue state fails to advance the queue because the target qTD is not active, or
If the Halted bit is a one on exit from the Fetch QH state.
The first portion of the buffer must begin at some offset in a page and extend through the end of
the page.
The remaining buffer cannot be allocated in small chunks scattered around memory. For each 4K
chunk beyond the first page, each buffer portion matches to a full 4K page. The final portion, which
may only be large enough to occupy a portion of a page, must start at the top of the page and be
contiguous within that page.
Follow Queue Head Horizontal Pointer
Buffer Pointer List Use for Data Streaming with qTDs
illustrates these requirements.
MPC5125 Microcontroller Reference Manual, Rev. 2
Universal Serial Bus Interface with On-The-Go
32-109

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