MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 108

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Clocks and Low-Power Modes
1
2
3
5.3.1.1
Figure 5-6
reset configuration word low loaded during the reset flow. This register is updated during a power up
PORESET sequence.
1
5-8
Address: Base + 0x00
(0xFF40_0F00)
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
In this column, the symbol “U” indicates one or more bits in a byte are undefined at reset. See the associated description for
more information.
Reset value is indeterminate.
The reset value is defined by the latched reset configuration word (RST_CONF). See
CLOCK_BASE
Reset
Reset
Offset from
0x94–0xFF
W
W
0x90
R
R
16
shows the system PLL mode register. This is a read only register that retrieves its values from
0
0
0
0
0
System PLL Mode Register (SPMR)
1
17
0
0
0
0
1
System PLL lock counter (SPLL_LOCK_CNT)
Reserved
Table 5-5. Clock Configuration Registers memory map (continued)
18
0
0
0
0
2
19
0
0
0
0
3
Figure 5-6. System PLL Mode Register (SPMR)
MPC5125 Microcontroller Reference Manual, Rev. 2
—
20
4
0
0
1
Register
—
21
0
0
5
SPMF
1
—
22
0
0
6
1
—
23
0
0
7
1
24
8
0
0
0
0
25
9
0
0
0
0
Chapter 2, “System Configuration and Memory
Access
10
26
0
0
0
0
R
Table
11
27
0
0
0
0
0x000U_UUUU
4-2.
Reset Value
—
12
28
0
0
Freescale Semiconductor
1
Access: User read/write
—
2
13
29
0
0
CPMF
1
Section/Page
5.3.1.28/5-35
—
14
30
0
0
1
—
15
31
0
0
1