MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 745

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

26.2.1.7
26.2.1.8
Freescale Semiconductor
FIFO START ADDRESS Defines the word start address for this FIFO slice. The software must take care not to allow overlap
WRITE POINTER Write Pointer. This read-only register shows the current write position in the FIFO memory without the offset
Address: Base + 0x98 (PSCn_TX_PTR)
Address: Base + 0x9C (PSCn_TX_SIZE)
READ POINTER Read Pointer. This read-only register shows the current read position in the FIFO memory without the offset
Reset
Reset
Reset
Reset
Field
W
W
W
W
FIFO SIZE
R
R
R
R
Field
Base + 0xD8 (PSCn_RX_PTR)
Base + 0xDC (PSCn_RX_SIZE)
16
16
0
0
0
0
0
0
0
0
0
0
Pointer Register (PTR)
FIFO Size Register (SIZE)
17
17
0
0
0
0
0
0
0
0
1
1
for the slice number. This register is writeable during debug mode.
for the slice number. This register is writeable during debug mode.
in the memory areas to appear.
Defines the size (number of words) of this FIFO slice.
18
18
0
0
0
0
0
0
0
0
2
2
19
19
0
0
0
0
0
0
3
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Figure 26-9. FIFO Size Register (SIZE)
20
20
4
0
0
4
0
0
0
0
Table 26-11. SIZE field descriptions
Figure 26-8. Pointer Register (PTR)
Table 26-10. PTR field descriptions
21
21
0
0
0
0
0
5
5
22
22
0
0
0
0
6
6
23
23
0
0
0
0
7
7
Description
Description
WRITE POINTER
24
READ POINTER
24
8
0
0
8
0
0
FIFO START ADDRESS
25
25
9
0
0
9
0
0
FIFO SIZE
10
26
10
26
0
0
0
0
PSC Centralized FIFO Controller (FIFOC)
Access: User read-only / Debug write
11
27
11
27
0
0
0
0
12
28
12
28
0
0
0
0
Access: User read/write
13
29
13
29
0
0
0
0
14
30
14
30
0
0
0
0
26-11
15
31
15
31
0
0
0
0