MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 460

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Integrated Programmable Interrupt Controller (IPIC)
18-12
Address: Base + 0x08
USB2OTG1
USB2OTG2
Reset
Reset
SDHC2
SDHC1
GPT10
GPT11
FIFOC
PSC4
PSC5
PSC6
PSC7
PSC8
PSC9
GPT8
GPT9
FEC1
FEC2
Field
NFC
LPC
W
W
R
R
PSC4 PSC5 PSC6 PSC7 PSC8 PSC9 GPT8 GPT9 FIFOC
16
0
0
0
Figure 18-4. System Internal Interrupt Pending Register High (IPIC_SIPNR_H)
PSC4 internal interrupt source. When an interrupt is received, the interrupt controller sets the corresponding
IPIC_SIPNRx bit. When a pending interrupt is managed, clear the corresponding IPIC_SIPNRx bit. However,
if an event register exists, the unmasked event register bits should be cleared instead, causing the
IPIC_SIPNRx bit to be cleared.
IPIC_SIPNRx bits are read-only. Writing to this register has no effect.
Note: The IPIC_SIPNRx bit positions are not changed according to their relative priority.
PSC5 internal interrupt source.
PSC6 internal interrupt source.
PSC7 internal interrupt source.
PSC8 internal interrupt source.
PSC9 internal interrupt source.
GPT8 internal interrupt source.
GPT9 internal interrupt source.
FIFOC internal interrupt source.
USB2OTG1 internal interrupt source.
USB2OTG2 internal interrupt source.
GPT10 internal interrupt source.
GPT11 internal interrupt source.
SDCH2 internal interrupt source.
FEC1 internal interrupt source.
FEC2 internal interrupt source.
NFC internal interrupt source.
LPC internal interrupt source.
SDHC1 internal interrupt source.
17
0
0
1
18
0
0
2
FEC1 FEC2 NFC
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-5. IPIC_SIPNR_H field descriptions
20
4
0
0
21
0
0
5
LPC
22
0
0
6
23
0
0
7
Description
I2C1
24
8
0
0
I2C2
25
9
0
0
0
I2C3
10
26
0
0
0
OTG1
USB2
11
27
0
0
OTG2
USB2
12
28
0
0
Freescale Semiconductor
Access: User read-only
BDLC GPT0 GPT1
13
29
0
0
0
14
30
0
0
0
15
31
0
0
0