MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 738

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PSC Centralized FIFO Controller (FIFOC)
1
26-4
PSC0: 0xFF41_1000
PSC1: 0xFF41_1100
PSC2: 0xFF41_1200
PSC3: 0xFF41_1300
PSC4: 0xFF41_1400
PSC5: 0xFF41_1500
PSC6: 0xFF41_1600
PSC7: 0xFF41_1700
PSC8: 0xFF41_1800
PSC9: 0xFF41_1900
Default absolute offset with IMMRBAR at default location of 0xFF40_0000. See
Map (XLBMEN + Mem Map).”
PSC_BASE
Offset from
0xA0–0xBB
0xE0–0xEB
0x00–0x54
0x58–0x7F
0xCC
0xDC
0x9C
0xBC
0xFC
0x8C
0xC0
0xC4
0xC8
0xD0
0xD4
0xD8
0x80
0x84
0x88
0x90
0x94
0x98
1
PSC registers. See
Reserved
Command register for PSCn TX slice (PSCn_TX_CMD)
Alarm level for PSCn TX slice (PSCn_TX_ALARM)
Status register for PSCn TX slice (PSCn_TX_SR)
Interrupt status register for PSCn TX slice (PSCn_TX_ISR)
Interrupt mask register for PSCn TX slice (PSCn_TX_IMR)
FIFO count for PSCn TX slice (PSCn_TX_COUNT)
FIFO pointer for PSCn TX slice (PSCn_TX_POINTER)
FIFO size register for PSCn TX slice (PSCn_TX_SIZE)
Reserved
FIFO data register for PSCn TX slice (PSCn_TX_DATA)
Command register for PSCn RX slice (PSCn_RX_CMD)
Alarm level for PSCn RX slice (PSCn_RX_ALARM)
Status register for PSCn RX slice (PSCn_RX_STAT)
Interrupt status register for PSCn RX slice (PSCn_RX_ISR)
Interrupt mask register for PSCn RX slice (PSCn_RX_IMR)
FIFO count for PSCn RX slice (PSCn_RX_COUNT)
FIFO pointer for PSCn RX slice (PSCn_RX_POINTER)
FIFO size register for PSCn RX slice (PSCn_RX_SIZE)
Reserved
FIFO data register for PSCn RX slice (PSCn_RX_DATA)
MPC5125 Microcontroller Reference Manual, Rev. 2
Chapter 25, “Programmable Serial Controller (PSC).”
Table 26-2. PSC memory map
Register
Chapter 2, “System Configuration and Memory
Access Reset Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
0x0000_0000
0x0000_0000
0x0000_0080
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0080
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Freescale Semiconductor
26.2.1.6/26-10
26.2.1.7/26-11
26.2.1.8/26-11
26.2.1.9/26-12
26.2.1.6/26-10
26.2.1.7/26-11
26.2.1.8/26-11
26.2.1.9/26-12
Section/Page
26.2.1.1/26-5
26.2.1.2/26-6
26.2.1.3/26-7
26.2.1.4/26-8
26.2.1.5/26-9
26.2.1.1/26-5
26.2.1.2/26-6
26.2.1.3/26-7
26.2.1.4/26-8
26.2.1.5/26-9