MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 974

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Interface with On-The-Go
32.6.14.2.3 Interrupt on Async Advance
This event is used for deterministic removal of queue heads from the asynchronous schedule. When the
host controller advances the on-chip context of the asynchronous schedule, it evaluates the value of the
interrupt on async advance doorbell bit in the USB_USBCMD register. If it is set, it sets the interrupt on
async advance bit in the USB_USBSTS register. If the interrupt on async advance enable bit in the
USB_USBINTR register is set, the host controller issues a hardware interrupt at the next interrupt
threshold. A detailed explanation of this feature is described in
from Asynchronous Schedule.”
32.6.14.2.4 Host System Error
The host controller is a bus master and any interaction between the host controller and the system may
experience errors. The type of host error may be catastrophic to the host controller making it impossible
for the host controller to continue in a coherent fashion. Behavior for these types of errors is to halt the
host controller. Host-based error must result in the following actions:
Table 32-82
32-146
•
•
•
The run/stop bit in the USB_USBCMD register is cleared.
The host system error and HCHalted bits in the USB_USBSTS register are set.
If the host system error enable bit in the USB_USBINTR register is set, the host controller issues
a hardware interrupt. This interrupt is not delayed to the next interrupt threshold.
summarizes the required actions taken on the various host errors.
Frame list pointer fetch (read)
siTD fetch (read)
siTD status write-back (write)
iTD fetch (read)
iTD status write-back (write)
qTD fetch (read)
qHD status write-back (write)
Data write
Data read
After a host system error, software must reset the host controller using
HCReset in the USB_USBCMD register before re-initializing and restarting
the host controller.
Cycle Type
Table 32-82. Summary Behavior on Host System Errors
MPC5125 Microcontroller Reference Manual, Rev. 2
Master Abort
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
NOTE
Target Abort
Section 32.6.7.2, “Removing Queue Heads
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Data Phase Parity
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
Fatal
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