MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 883

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

32.3.2
Both USB controllers contain local DMA engines. The DMA Engine interface is responsible for moving
all of the data to transfer over the USB between the controller and buffers in system memory. Like the
system interface block, the DMA engine block uses a simple synchronous bus signaling protocol.
The DMA controllers must access both control information and packet data from system memory. The
control information is contained in link-list based queue structures. The DMA controllers have state
machines able to parse data structures defined in the EHCI specification. In host mode, the data structures
are EHCI compliant and represent queues of transfers performed by the host controller. In device mode,
the data structures are similar to those in the EHCI specification and allow device responses to be queued
for each of the active pipes in the device.
32.3.3
The FIFO RAM controller is for context information and to control FIFOs between the protocol engine
and the DMA controller. These FIFOs decouple the system processor/memory bus requests from the
extremely tight timing required by USB.
The use of the FIFO buffers differs between host and device mode operation. In host mode, a single data
channel is maintained in each direction through the buffer memory. In device mode, multiple FIFO
channels are maintained for each of the active endpoints in the system.
For both modules (USB1 and USB2) device operation uses a single 256-byte RX buffer and a 512-byte
TX buffer for each endpoint. The 512-byte buffers allow the modules to buffer a complete HS bulk packet.
The USB1 and USB2 module interfaces to ULPI compatible PHY. The primary function of the port
controller block is to isolate the rest of the module from the transceiver and to move all of the transceiver
signaling into the primary clock domain of the module. This allows the module to run synchronously with
the system processor and it's associated resources.
32.4
32.4.1
In the previous section, the register interface has behaviors described for device and host mode. However,
during OTG operations, it is necessary to perform tasks independent of the controller mode.
Freescale Semiconductor
OTG Operations
DMA Engine
FIFO RAM Controller
Register Bits
MPC5125 Microcontroller Reference Manual, Rev. 2
Universal Serial Bus Interface with On-The-Go
32-55