MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 778

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Secure Digital Host Controller (SDHC)
28-6
Address: Base + 0x04
YBUF_EMPTY Y Data Buffer Empty. When this is set, it indicates the Y data buffer is empty during a write transfer. This bit is
XBUF_EMPTY X Data Buffer Empty. When set, this bit indicates the X data buffer is empty during a write transfer. This bit is
YBUF_FULL
INSERTION
REMOVAL
Reset
Reset
CARD_
CARD_
Field
W w1c
W
R CARD_
R
INSER
TION
16
0
0
0
0
CARD_
SDIO_
ACTIVE
REMO
Card Insertion. When this bit is set, the SDHC detects a value transition on the DAT[3:0] from b0111 to b1111.
This can detect whether a card is inserted to the card socket based on DAT3 pull-up resistor of the card DAT3.
When this bit is set, the SDHC generates an interrupt request if the card detection interrupt is enabled. This
bit is read-only and can be cleared by writing 1 to this bit.
0 No card insertion detected.
1 Card insertion detected based on logic level changed on DAT3.
Card Removal. When this bit is set, the SDHC detects a logic transition on the DAT[3:0] from b1111 to b0111.
This can detect whether a card is removed from the card socket based on the DAT3 pull-up resistor of the card
DAT3. When this bit is set, the SDHC generates an interrupt request if the card removal interrupt is enabled.
This bit is read-only and can be cleared by writing a 1 to it. Software needs to clear this bit to clear the interrupt
request from SDHC when card detection interrupt is enabled.
0 No card insertion detected.
1 Card removal detected based on logic level changed on DAT3.
automatically cleared when the first byte of data is moved into the FIFO. Refer to
Buffers,”
0 Y buffer is not empty.
1 Y buffer is empty.
automatically cleared when the first byte of data is moved into the FIFO. Refer to
Buffers,”
0 X buffer is not empty.
1 X buffer is empty.
Y Data Buffer Full. When set, this bit indicates the Y data buffer is full during a read transfer. This bit is
automatically cleared when the last byte of data is read out from the FIFO. Refer to
Buffers,”
0 Y buffer is not full.
1 Y buffer is full.
INT_
w1c
w1c
VAL
17
0
0
1
EMPTY
YBUF_
CMD_
END_
RESP
w1c
for more information about the data buffers
for more information about the data buffers.
for more information about the data buffers.
18
0
0
2
XBUF_
EMPTY
WRITE
Figure 28-3. SDHC Status (SDHC_STATUS) Register
DONE
_OP_
w1c
19
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 28-5. SDHC_STATUS field descriptions
YBUF_
DONE
READ
_OP_
FULL
w1c
20
4
0
0
_FULL
XBUF
WR_CRC_ER
w1c
21
0
R_CODE
0
5
UND_
BUF_
RUN
w1c
22
0
0
6
_CLK_
CARD
_BUS
BUF_
OVFL
RUN
23
0
0
7
Description
READ
_RDY
BUF_
.
24
8
0
0
0
BUF_
WR_
RDY
25
9
0
0
0
RESP
_CRC
_ERR
w1c
10
26
0
0
0
w1c
11
27
0
0
0
0
READ
_CRC
_ERR
w1c
Section 28.4.1, “Data
Section 28.4.1, “Data
12
28
0
0
0
Freescale Semiconductor
Section 28.4.1, “Data
Access: User read/write
WRITE
_CRC
_ERR
w1c
13
29
0
0
0
TIME_
OUT_
RESP
w1c
14
30
0
0
0
TIME_
OUT_
READ
w1c
15
31
0
0
0