MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 467

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
USB2OTG1
USB2OTG2
MSCAN1
MSCAN2
SDHC2
SDHC1
GPT10
GPT11
FIFOC
PSC4
PSC5
PSC6
PSC7
PSC8
PSC9
GPT8
GPT9
FEC1
FEC2
BDLC
GPT0
GPT1
Field
NFC
I2C1
I2C2
I2C3
LPC
PSC4 external interrupt source. Mask an interrupt by clearing the IPIC_SIMSRx bit. An interrupt can be
enabled by setting the corresponding IPIC_SIMSRx bit. The IPIC_SIMSRx can be read at any time.
Note:
PSC5 external interrupt source.
PSC6 external interrupt source.
PSC7 external interrupt source.
PSC8 external interrupt source.
PSC9 external interrupt source.
GPT8 external interrupt source.
GPT9 external interrupt source.
FIFOC external interrupt source.
USB2OTG1 external interrupt source.
USB2OTG2 external interrupt source.
GPT10 external interrupt source.
GPT11 external interrupt source.
SDCH2 external interrupt source.
FEC1 external interrupt source.
FEC2 external interrupt source.
NFC external interrupt source.
LPC external interrupt source.
SDHC1 external interrupt source.
I2C1 external interrupt source.
I2C2 external interrupt source.
I2C3 external interrupt source.
MSCAN1 external interrupt source.
MSCAN2 external interrupt source.
BDLC external interrupt source.
GPT0 external interrupt source.
GPT1 external interrupt source.
• IPIC_SIMSRx bit positions are not changed according to their relative priority.
• Pending register bits set by multiple interrupt events can be cleared only by clearing all unmasked events
• If an IPIC_SIMSRx bit is masked at the same time the corresponding IPIC_SIPNRx bit causes an interrupt
in the corresponding event register.
request to the core, the error vector is issued (if no other interrupts pending). Therefore, always include an
error.
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-11. IPIC_SIMSR_H field descriptions
Description
Integrated Programmable Interrupt Controller (IPIC)
18-19