MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 698

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programmable Serial Controller (PSC)
25.4.1.11 Interrupt Mask Register (IMR)
The IMR register selects corresponding bits in the ISR that cause an interrupt.
25-20
UNEX_RX_SLOT AC97 Mode. Unexpected RX Slots detect
Address: Base + 0x24
Address: Base + 0x24
DATA_VALID
CMD_SEND
DATA_OVR
Reset
Reset
•
•
Field
W
W
R
R
If one ISR bit is set and the corresponding IMR bit is also set, the internal interrupt output is
asserted.
If the corresponding bit in IMR is 0, the state of the ISR bit has no effect on the interrupt output.
The IMR does not mask reading the ISR.
IPC
IPC
0
0
0
0
AC97 Mode. Command Send ready
This bit is identical to the CMD_SEND bit in the SR register. To clear this interrupt use the reset error status
command in the CR register.
other Modes. Reserved.
AC97 Mode. Receive Data Overwrite
This bit is identical to the DATA_OVR bit in the SR register. To clear this interrupt, use the reset error status
command in the CR register.
Other Modes. Reserved.
AC97 Mode. Received Status Data
This bit is identical to the DATA_VALID bit in the SR register. To clear this interrupt, use the reset error status
command in the CR register.
Other Modes. Reserved.
This bit is identical to the UNEX_RX_SLOT bit in the SR register. To clear this interrupt, use the reset error
status command in the CR register.
Other Modes. Reserved.
0
0
0
0
1
1
0
0
0
0
Figure 25-25. Interrupt Mask Register for Other Modes (IMR)
2
2
Figure 25-24. Interrupt Mask Register for UART Mode (IMR)
ORE
ORE
RR
RR
0
0
3
3
Table 25-15. ISR field descriptions (continued)
MPC5125 Microcontroller Reference Manual, Rev. 2
TxEM
URE
RR
P
4
0
4
0
DB
0
0
0
5
5
0
0
0
0
6
6
0
0
0
0
7
7
Description
8
0
0
8
0
0
Error
Error
9
0
9
0
Time
Out
10
10
0
0
0
11
11
0
0
0
0
CMD_
SEND
12
12
0
0
0
Freescale Semiconductor
Access: User read/write
Access: User read/write
DATA_
OVR
13
13
0
0
0
DATA_
VALID
14
14
0
0
0
UNEX
_RX_
SLOT
15
15
0
0
0