MPC5125YVN400 Freescale Semiconductor, MPC5125YVN400 Datasheet - Page 461

• Manufacturer Part Number: MPC5125YVN400
• Description: IC MCU 32BIT E300 324TEPBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC51xxr

Specifications of MPC5125YVN400

• Core Processor: e300
• Core Size: 32-Bit
• Speed: 400MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, USB OTG
• Peripherals: DMA, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.33 V ~ 1.47 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 324-PBGA
• Processor Series: MPC51xx
• Core: e300
• Data Bus Width: 32 bit
• Development Tools By Supplier: TWR-MPC5125-KIT, TWR-SER, TWR-ELEV, TOWER
• Maximum Clock Frequency: 400 MHz
• Operating Supply Voltage: 1.4 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 3.3 V
• Interface Type: CAN, I2C
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 32 bit
• Cpu Speed: 400MHz
• Embedded Interface Type: CAN, I2C, SPI, UART, USB
• Digital Ic Case Style: TEPBGA
• No. Of Pins: 324
• Rohs Compliant: Yes
• Cpu Family: MPC5xx
• Device Core Size: 32b
• Frequency (max): 400MHz
• Total Internal Ram Size: 32KB
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 324
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Address: Base + 0x0C
Reset
Reset
MSCAN1
MSCAN2
BDLC
GPT0
GPT1
Field
I2C1
I2C2
I2C3
DMA2
PSC0
PSC1
PSC2
PSC3
GPT2
W
W
Field
R
R
DIU
ALAR
RTC
DIU
16
M
0
0
0
Figure 18-5. System Internal Interrupt Pending Register Low (IPIC_SIPNR_L)
I2C1 internal interrupt source.
I2C2 internal interrupt source.
I2C3 internal interrupt source.
MSCAN1 internal interrupt source.
MSCAN2 internal interrupt source.
BDLC internal interrupt source.
GPT0 internal interrupt source.
GPT1 internal interrupt source.
DMA
DDR
17
2
0
0
1
DIU internal interrupt source. When an interrupt is received, the interrupt controller sets the corresponding
IPIC_SIPNRx bit. When a pending interrupt is managed, clear the corresponding IPIC_SIPNRx bit.
However, if an event register exists, the unmasked event register bits should be cleared instead, causing
the IPIC_SIPNRx bit to be cleared.
IPIC_SIPNR bitsx are read-only. Writing to this register has no effect.
Note: The IPIC_SIPNRx bit positions are not changed according to their relative priority.
DMA2 internal interrupt source.
PSC0 internal interrupt source.
PSC1 internal interrupt source.
PSC2 internal interrupt source.
PSC3 internal interrupt source.
GPT2 internal interrupt source.
SBA
18
0
0
0
2
Table 18-5. IPIC_SIPNR_H field descriptions (continued)
PMC
19
0
0
0
3
MPC5125 Microcontroller Reference Manual, Rev. 2
Table 18-6. IPIC_SIPNR_L field descriptions
OTG1
PSC0 PSC1 PSC2 PSC3 GPT2 GPT3 GPT4 GPT5 GPT6 GPT7
USB2
WKU
20
P
4
0
0
OTG2
USB2
WKU
21
P
0
0
5
GPIO
22
0
2
0
6
105C
TEM
23
P
0
0
7
Description
Description
IIM
24
8
0
0
PRIO
MON
Integrated Programmable Interrupt Controller (IPIC)
25
9
0
0
MSC
AN3
10
26
0
0
MSC
AN4
11
27
0
0
12
28
0
0
Access: User read-only
13
29
0
0
GPIO
14
30
1
0
0
RTC
SEC
18-13
15
31
0
0